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Taiwan Academic Institutional Repository >
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"jou jing yang"
Showing items 81-90 of 110 (11 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:24:50Z |
Multiple-Fault Diagnosis Using Faulty-Region Identification
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Tasi, Meng-Jai; Chao, Mango C. -T.; Jou, Jing-Yang; Wu, Meng-Chen |
| 國立交通大學 |
2014-12-08T15:24:37Z |
FSM-based transaction-level functional coverage for interface compliance verification
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Su, Man-Yun; Shih, Che-Hua; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:24:37Z |
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication
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Chen, Chien-Hua; Lee, Geeng-Wei; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:24:33Z |
Thread Affinity Mapping for Irregular Data Access on Shared Cache GPGPU
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Kuo, Hsien-Kai; Chen, Kuan-Ting; Lai, Bo-Cheng Charles; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:22:04Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
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Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:46Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture Considering Inter-Island Delay
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Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:44Z |
Design-for-Debug Layout Adjustment for FIB Probing and Circuit Editing
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Chen, Kuo-An; Chang, Tsung-Wei; Wu, Meng-Chen; Chao, Mango C. -T.; Jou, Jing-Yang; Chen, Sonair |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Mixed Non-Rectangular Block Packing for Non-Manhattan Layout Architectures
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Wu, Meng-Chen; Chen, Hung-Ming; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Equivalence Checking of Scheduling with Speculative Code Transformations in High-Level Synthesis
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Lee, Chi-Hui; Shih, Che-Hua; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:16:40Z |
On-chip bus encoding for power minimization under delay constraint
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Lin, Tzu-Wei; Tu, Shang-Wei; Jou, Jing-Yang |
Showing items 81-90 of 110 (11 Page(s) Totally)
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