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Taiwan Academic Institutional Repository >
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"jou jing yang"
Showing items 86-95 of 110 (11 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:21:46Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture Considering Inter-Island Delay
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Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:44Z |
Design-for-Debug Layout Adjustment for FIB Probing and Circuit Editing
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Chen, Kuo-An; Chang, Tsung-Wei; Wu, Meng-Chen; Chao, Mango C. -T.; Jou, Jing-Yang; Chen, Sonair |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Mixed Non-Rectangular Block Packing for Non-Manhattan Layout Architectures
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Wu, Meng-Chen; Chen, Hung-Ming; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Equivalence Checking of Scheduling with Speculative Code Transformations in High-Level Synthesis
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Lee, Chi-Hui; Shih, Che-Hua; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:16:40Z |
On-chip bus encoding for power minimization under delay constraint
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Lin, Tzu-Wei; Tu, Shang-Wei; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:15:41Z |
RLC coupling-aware simulation and on-chip bus encoding for delay reduction
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Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:15:32Z |
An optimum algorithm for compacting error traces for efficient design error debugging
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Yen, Chia-Chih; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:15:02Z |
A tableless approach for high-level power modeling using neural networks
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Hsu, Chih-Yang; Hsieh, Wen-Tsan; Liu, Chien-Nan Jimmy; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:13:35Z |
Observability analysis on HDL descriptions for effective functional validation
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Jiang, Tai-Ying; Liu, Chien-Nan Jimmy; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:13:33Z |
Hybrid word-length optimization methods of pipelined FFT processors
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Wang, Cheng-Yeh; Kuo, Chih-Bin; Jou, Jing-Yang |
Showing items 86-95 of 110 (11 Page(s) Totally)
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