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"jou jy"
Showing items 16-25 of 67 (7 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:44:21Z |
Converter-free multiple-voltage scaling techniques for low-power CMOS digital design
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Yeh, YJ; Kuo, SY; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:00Z |
Unified functional decomposition via encoding for FPGA technology mapping
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Jiang, JH; Jou, JY; Huang, JD |
| 國立交通大學 |
2014-12-08T15:42:37Z |
On automatic-verification pattern generation for SoC with port-order fault model
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Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:42:08Z |
Bootstrap Monte Carlo with adaptive stratification for power estimation
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Huang, HL; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:53Z |
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model
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Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:36Z |
Automatic interconnection rectification for SoC design verification based on the port order fault model
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Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:17Z |
A design-for-verification technique for functional pattern reduction
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Liu, CNJ; Chen, IL; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:09Z |
Inductance modeling for on-chip interconnects
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Tu, SW; Shen, WZ; Chang, YW; Chen, TC; Jou, JY |
| 國立交通大學 |
2014-12-08T15:40:33Z |
An efficient power model for IP-level complex designs
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Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:39:32Z |
A divide-and-conquer-based algorithm for automatic simulation vector generation
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Yen, CC; Jou, JY; Chen, KC |
Showing items 16-25 of 67 (7 Page(s) Totally)
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