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Taiwan Academic Institutional Repository >
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"jou jy"
Showing items 21-30 of 67 (7 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:41:36Z |
Automatic interconnection rectification for SoC design verification based on the port order fault model
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Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:17Z |
A design-for-verification technique for functional pattern reduction
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Liu, CNJ; Chen, IL; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:09Z |
Inductance modeling for on-chip interconnects
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Tu, SW; Shen, WZ; Chang, YW; Chen, TC; Jou, JY |
| 國立交通大學 |
2014-12-08T15:40:33Z |
An efficient power model for IP-level complex designs
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Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:39:32Z |
A divide-and-conquer-based algorithm for automatic simulation vector generation
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Yen, CC; Jou, JY; Chen, KC |
| 國立交通大學 |
2014-12-08T15:39:16Z |
Simultaneous floorplan and buffer-block optimization
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Jiang, IHR; Chang, YW; Jou, JY; Chao, KY |
| 國立交通大學 |
2014-12-08T15:37:25Z |
Special section on nanoelectronic circuits and systems - Guest editorial
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Wu, PCY; Zaghloul, ME; Jou, JY |
| 國立交通大學 |
2014-12-08T15:37:24Z |
Efficient vector compaction methods for power estimation with consecutive sampling techniques
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Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:27:41Z |
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping
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Huang, JD; Jou, JY; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:27:39Z |
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture
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Jiang, JH; Jou, JY; Huang, JD; Wei, JS |
Showing items 21-30 of 67 (7 Page(s) Totally)
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