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Taiwan Academic Institutional Repository >
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"jou jy"
Showing items 41-50 of 67 (7 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:26:47Z |
An improved AVPG algorithm for SoC design verification using port order fault model
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Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:45Z |
An efficient design-for-verification technique for HDLs
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Liu, CNJ; Chen, IL; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:28Z |
Effective error diagnosis for RTL designs in HDLS
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Jiang, TY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:21Z |
Improved vector compaction for power estimation with multi-sequence sampling technique
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Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:15Z |
SOC design integration by using automatic interconnection rectification
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Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:11Z |
An automatic interconnection rectification technique for SoC design integration
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Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:11Z |
An efficient IP-Level power model for complex digital circuits
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Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:04Z |
An efficient approach for error diagnosis in HDL design
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Shi, CH; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:57Z |
RLC effects on worst-case switching pattern for on-chip buses
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Tu, SW; Jou, JY; Chang, YW |
| 國立交通大學 |
2014-12-08T15:25:57Z |
An efficient approach for hierarchical submodule extraction
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Lin, YW; Jou, JY |
Showing items 41-50 of 67 (7 Page(s) Totally)
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