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"jou jy"
Showing items 51-60 of 67 (7 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:25:57Z |
An efficient logic extraction algorithm using partitioning and circuit encoding
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Huang, L; Jiang, TY; Jou, JY; Huang, HL |
| 國立交通大學 |
2014-12-08T15:25:49Z |
Verification on port connections
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Lee, GW; Wang, CY; Huang, JD; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:43Z |
Enhancing sequential depth computation with a branch-and-bound algorithm
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Yen, CC; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:42Z |
Graph automorphism-based algorithm for determining symmetric inputs
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Chou, CL; Wang, CY; Lee, GW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:40Z |
Layout techniques for on-chip interconnect inductance reduction
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Tu, SW; Jou, JY; Chang, YW |
| 國立交通大學 |
2014-12-08T15:25:40Z |
Optimal design of high fan-in multiplexers via mixed-integer nonlinear programming
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Huang, HW; Wang, CY; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:40Z |
On compliance test of on-chip bus for SOC
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Lin, HM; Yen, CC; Shih, CH; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:38Z |
Formal compliance verification of interface protocols
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Yang, YC; Huang, JD; Yen, CC; Shih, CH; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:38Z |
On-chip bus encoding for LC cross-talk reduction
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Huang, JS; Tu, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:24Z |
RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction
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Tu, SW; Jou, JY; Chang, YW |
Showing items 51-60 of 67 (7 Page(s) Totally)
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