| 國立交通大學 |
2014-12-08T15:27:36Z |
A power modeling and characterization method for the CMOS standard cell library
|
Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:27:29Z |
A power modeling and characterization method for macrocells using structure information
|
Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:27:27Z |
Power driven partial scan
|
Jou, JY; Nien, MC |
| 國立交通大學 |
2014-12-08T15:27:20Z |
Compatible class encoding in hyper-function decomposition for FPGA synthesis
|
Jiang, JHR; Jou, JY; Huang, JD |
| 國立交通大學 |
2014-12-08T15:27:12Z |
Hierarchical floorplan design on the Internet
|
Lin, JH; Jou, JY; Jiang, HR |
| 國立交通大學 |
2014-12-08T15:26:58Z |
A novel approach for functional coverage measurement in HDL
|
Liu, CNJ; Chang, CY; Jou, JY; Lai, MC; Juan, HM |
| 國立交通大學 |
2014-12-08T15:26:54Z |
Title on flip-flop inference in HDL synthesis
|
Lin, HM; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:53Z |
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model
|
Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:51Z |
Automatic functional vector generation using the interacting FSM model
|
Liu, CNJ; Yen, CC; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:50Z |
On placement and routing of wafer scale memory
|
Sung, LA; Jiang, IHR; Chang, YW; Jou, JY; Wu, JC; Feng, TS |
| 國立交通大學 |
2014-12-08T15:26:47Z |
An improved AVPG algorithm for SoC design verification using port order fault model
|
Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:45Z |
An efficient design-for-verification technique for HDLs
|
Liu, CNJ; Chen, IL; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:28Z |
Effective error diagnosis for RTL designs in HDLS
|
Jiang, TY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:21Z |
Improved vector compaction for power estimation with multi-sequence sampling technique
|
Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:15Z |
SOC design integration by using automatic interconnection rectification
|
Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:11Z |
An automatic interconnection rectification technique for SoC design integration
|
Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:11Z |
An efficient IP-Level power model for complex digital circuits
|
Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:26:04Z |
An efficient approach for error diagnosis in HDL design
|
Shi, CH; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:57Z |
RLC effects on worst-case switching pattern for on-chip buses
|
Tu, SW; Jou, JY; Chang, YW |
| 國立交通大學 |
2014-12-08T15:25:57Z |
An efficient approach for hierarchical submodule extraction
|
Lin, YW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:57Z |
An efficient logic extraction algorithm using partitioning and circuit encoding
|
Huang, L; Jiang, TY; Jou, JY; Huang, HL |
| 國立交通大學 |
2014-12-08T15:25:49Z |
Verification on port connections
|
Lee, GW; Wang, CY; Huang, JD; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:43Z |
Enhancing sequential depth computation with a branch-and-bound algorithm
|
Yen, CC; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:42Z |
Graph automorphism-based algorithm for determining symmetric inputs
|
Chou, CL; Wang, CY; Lee, GW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:25:40Z |
Layout techniques for on-chip interconnect inductance reduction
|
Tu, SW; Jou, JY; Chang, YW |
