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"jou jy"的相關文件
顯示項目 1-25 / 67 (共3頁)
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| 國立交通大學 |
2014-12-08T15:49:17Z |
Static power analysis for power-driven synthesis
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Yuan, SY; Chen, KH; Jou, JY; Kuo, SY |
| 國立交通大學 |
2014-12-08T15:48:55Z |
Sensitisable-path-oriented clustered voltage scaling technique for low power
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Jou, JY; Chou, DS |
| 國立交通大學 |
2014-12-08T15:48:51Z |
Power-oriented partial-scan design approach
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Jou, JY; Nien, MC |
| 國立交通大學 |
2014-12-08T15:48:47Z |
Special issue on hardware description languages - Foreword
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Jou, JY; Lin, YL |
| 國立交通大學 |
2014-12-08T15:48:47Z |
A logical fault model for library coherence checking
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Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:47:21Z |
On circuit clustering for area/delay tradeoff under capacity and pin constraints
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Huang, JD; Jou, JY; Shen, WZ; Chuang, HH |
| 國立交通大學 |
2014-12-08T15:46:14Z |
A structure-oriented power modeling technique for macrocells
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Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:46:03Z |
Internet-based hierarchical floorplan design
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Lin, JH; Jou, JY; Jiang, IHR |
| 國立交通大學 |
2014-12-08T15:45:37Z |
On computing the minimum feedback vertex set of a directed graph by contraction operations
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Lin, HM; Jou, JY |
| 國立交通大學 |
2014-12-08T15:45:10Z |
An automatic controller extractor for HDL descriptions at the RTL
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Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:59Z |
ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping
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Huang, JD; Jou, JY; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:44:51Z |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
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Jiang, IHR; Chang, YW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:35Z |
Delay-optimal technology mapping for hard-wired non-homogeneous FPGAs
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Chuang, HH; Jou, JY; Shung, CB |
| 國立交通大學 |
2014-12-08T15:44:32Z |
A new method for constructing IP level power model based on power sensitivity
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Huang, HL; Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:23Z |
Efficient coverage analysis metric for HDL design validation
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Liu, CN; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:21Z |
Converter-free multiple-voltage scaling techniques for low-power CMOS digital design
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Yeh, YJ; Kuo, SY; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:00Z |
Unified functional decomposition via encoding for FPGA technology mapping
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Jiang, JH; Jou, JY; Huang, JD |
| 國立交通大學 |
2014-12-08T15:42:37Z |
On automatic-verification pattern generation for SoC with port-order fault model
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Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:42:08Z |
Bootstrap Monte Carlo with adaptive stratification for power estimation
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Huang, HL; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:53Z |
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model
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Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:36Z |
Automatic interconnection rectification for SoC design verification based on the port order fault model
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Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:17Z |
A design-for-verification technique for functional pattern reduction
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Liu, CNJ; Chen, IL; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:09Z |
Inductance modeling for on-chip interconnects
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Tu, SW; Shen, WZ; Chang, YW; Chen, TC; Jou, JY |
| 國立交通大學 |
2014-12-08T15:40:33Z |
An efficient power model for IP-level complex designs
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Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:39:32Z |
A divide-and-conquer-based algorithm for automatic simulation vector generation
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Yen, CC; Jou, JY; Chen, KC |
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