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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
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Showing items 41-50 of 67  (7 Page(s) Totally)
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Institution Date Title Author
國立交通大學 2014-12-08T15:26:47Z An improved AVPG algorithm for SoC design verification using port order fault model Wang, CY; Tung, SW; Jou, JY
國立交通大學 2014-12-08T15:26:45Z An efficient design-for-verification technique for HDLs Liu, CNJ; Chen, IL; Jou, JY
國立交通大學 2014-12-08T15:26:28Z Effective error diagnosis for RTL designs in HDLS Jiang, TY; Liu, CNJ; Jou, JY
國立交通大學 2014-12-08T15:26:21Z Improved vector compaction for power estimation with multi-sequence sampling technique Hsu, CY; Liu, CNJ; Jou, JY
國立交通大學 2014-12-08T15:26:15Z SOC design integration by using automatic interconnection rectification Wang, CY; Tung, SW; Jou, JY
國立交通大學 2014-12-08T15:26:11Z An automatic interconnection rectification technique for SoC design integration Wang, CY; Tung, SW; Jou, JY
國立交通大學 2014-12-08T15:26:11Z An efficient IP-Level power model for complex digital circuits Hsu, CY; Liu, CNJ; Jou, JY
國立交通大學 2014-12-08T15:26:04Z An efficient approach for error diagnosis in HDL design Shi, CH; Jou, JY
國立交通大學 2014-12-08T15:25:57Z RLC effects on worst-case switching pattern for on-chip buses Tu, SW; Jou, JY; Chang, YW
國立交通大學 2014-12-08T15:25:57Z An efficient approach for hierarchical submodule extraction Lin, YW; Jou, JY

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