| 國立交通大學 |
2014-12-08T15:47:21Z |
On circuit clustering for area/delay tradeoff under capacity and pin constraints
|
Huang, JD; Jou, JY; Shen, WZ; Chuang, HH |
| 國立交通大學 |
2014-12-08T15:46:14Z |
A structure-oriented power modeling technique for macrocells
|
Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:46:03Z |
Internet-based hierarchical floorplan design
|
Lin, JH; Jou, JY; Jiang, IHR |
| 國立交通大學 |
2014-12-08T15:45:37Z |
On computing the minimum feedback vertex set of a directed graph by contraction operations
|
Lin, HM; Jou, JY |
| 國立交通大學 |
2014-12-08T15:45:10Z |
An automatic controller extractor for HDL descriptions at the RTL
|
Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:59Z |
ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping
|
Huang, JD; Jou, JY; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:44:51Z |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
|
Jiang, IHR; Chang, YW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:35Z |
Delay-optimal technology mapping for hard-wired non-homogeneous FPGAs
|
Chuang, HH; Jou, JY; Shung, CB |
| 國立交通大學 |
2014-12-08T15:44:32Z |
A new method for constructing IP level power model based on power sensitivity
|
Huang, HL; Lin, JY; Shen, WZ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:23Z |
Efficient coverage analysis metric for HDL design validation
|
Liu, CN; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:21Z |
Converter-free multiple-voltage scaling techniques for low-power CMOS digital design
|
Yeh, YJ; Kuo, SY; Jou, JY |
| 國立交通大學 |
2014-12-08T15:44:00Z |
Unified functional decomposition via encoding for FPGA technology mapping
|
Jiang, JH; Jou, JY; Huang, JD |
| 國立交通大學 |
2014-12-08T15:42:37Z |
On automatic-verification pattern generation for SoC with port-order fault model
|
Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:42:08Z |
Bootstrap Monte Carlo with adaptive stratification for power estimation
|
Huang, HL; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:53Z |
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model
|
Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:36Z |
Automatic interconnection rectification for SoC design verification based on the port order fault model
|
Wang, CY; Tung, SW; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:17Z |
A design-for-verification technique for functional pattern reduction
|
Liu, CNJ; Chen, IL; Jou, JY |
| 國立交通大學 |
2014-12-08T15:41:09Z |
Inductance modeling for on-chip interconnects
|
Tu, SW; Shen, WZ; Chang, YW; Chen, TC; Jou, JY |
| 國立交通大學 |
2014-12-08T15:40:33Z |
An efficient power model for IP-level complex designs
|
Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:39:32Z |
A divide-and-conquer-based algorithm for automatic simulation vector generation
|
Yen, CC; Jou, JY; Chen, KC |
| 國立交通大學 |
2014-12-08T15:39:16Z |
Simultaneous floorplan and buffer-block optimization
|
Jiang, IHR; Chang, YW; Jou, JY; Chao, KY |
| 國立交通大學 |
2014-12-08T15:37:25Z |
Special section on nanoelectronic circuits and systems - Guest editorial
|
Wu, PCY; Zaghloul, ME; Jou, JY |
| 國立交通大學 |
2014-12-08T15:37:24Z |
Efficient vector compaction methods for power estimation with consecutive sampling techniques
|
Hsu, CY; Liu, CNJ; Jou, JY |
| 國立交通大學 |
2014-12-08T15:27:41Z |
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping
|
Huang, JD; Jou, JY; Shen, WZ |
| 國立交通大學 |
2014-12-08T15:27:39Z |
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture
|
Jiang, JH; Jou, JY; Huang, JD; Wei, JS |
