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Taiwan Academic Institutional Repository >
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"jou shyh jye"
Showing items 141-150 of 182 (19 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:32:50Z |
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design
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Wang, Li-Rong; Tu, Ming-Hsien; Jou, Shyh-Jye; Lee, Chung-Len |
| 國立交通大學 |
2014-12-08T15:32:18Z |
A Low-Overhead Interference Canceller for High-Mobility STBC-OFDM Systems
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Chen, Hsiao-Yun; Chang, Wei-Kai; Jou, Shyh-Jye |
| 國立交通大學 |
2014-12-08T15:32:16Z |
A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band
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Liu, Wei-Chang; Yeh, Fu-Chun; Wei, Ting-Chen; Chan, Ching-Da; Jou, Shyh-Jye |
| 國立交通大學 |
2014-12-08T15:30:07Z |
Testing Strategies for a 9T Sub-threshold SRAM
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Yang, Hao-Yu; Lin, Chen-Wei; Chen, Hung-Hsin; Chao, Mango C. -T.; Tu, Ming-Hsien; Jou, Shyh-Jye; Chuang, Ching-Te |
| 國立交通大學 |
2014-12-08T15:30:06Z |
High-Performance 0.6V V-MIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder
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Yang, Hao-I; Lin, Yi-Wei; Hsia, Mao-Chih; Lin, Geng-Cing; Chang, Chi-Shin; Chen, Yin-Nien; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Lien, Nan-Chun; Li, Hung-Yu; Lee, Kuen-Di; Shih, Wei-Chiang; Wu, Ya-Ping; Lee, Wen-Ta; Hsu, Chih-Chiang |
| 國立交通大學 |
2014-12-08T15:30:06Z |
An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array
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Lin, Geng-Cing; Wang, Shao-Cheng; Lin, Yi-Wei; Tsai, Ming-Chien; Chuang, Ching-Te; Jou, Shyh-Jye; Lien, Nan-Chun; Shih, Wei-Chiang; Lee, Kuen-Di; Chu, Jyun-Kai |
| 國立交通大學 |
2014-12-08T15:30:04Z |
A 80-uW 2-Mb/s Transceiver for Human Body Channel Binaural Communication
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Sun, Jhih-Cing; Chen, Jou-Ling; Shen, Yi-Hung; You, Shiu-Chain; Jou, Shyh-Jye; Sang, Tzu-Hsien |
| 國立交通大學 |
2014-12-08T15:30:04Z |
A Low-Power Body-Channel Communication System for Binaural Hearing Aids
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Chen, Jou-Ling; Sun, Jhih-Cing; Shen, Yi-Hung; Sang, Tzu-Hsien; Chang, Tian-Sheuan; Jou, Shyh-Jye |
| 國立交通大學 |
2014-12-08T15:30:03Z |
Design and Implementation of Dynamic Word-Line Pulse Write Margin Monitor for SRAM
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Wang, Shao-Cheng; Lin, Geng-Cing; Lin, Yi-Wei; Tsai, Ming-Chien; Chiu, Yi-Wei; Jou, Shyh-Jye; Chuang, Ching-Te; Lien, Nan-Chun; Shih, Wei-Chiang; Lee, Kuen-Di; Chu, Jyun-Kai |
| 國立交通大學 |
2014-12-08T15:29:40Z |
A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
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Lu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
Showing items 141-150 of 182 (19 Page(s) Totally)
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