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"jou yn"
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| 國立交通大學 |
2014-12-08T15:48:52Z |
A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up
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Chen, MJ; Lee, HS; Chen, JH; Hou, CS; Lin, CS; Jou, YN |
| 國立交通大學 |
2014-12-08T15:02:35Z |
Back-gate forward bias method for low-voltage CMOS digital circuits
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Chen, MJ; Ho, JS; Huang, TH; Yang, CH; Jou, YN; Wu, T |
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