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"jri lee"的相關文件
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| 臺大學術典藏 |
2020-06-11T07:06:12Z |
Tutorial: "Design of high-speed wireline transceivers".
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Lee, Jri; Lee, Jri; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:12Z |
A 94GHz duobinary keying wireless transceiver in 65nm CMOS
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Chen, Y.-L.;Kao, C.;Peng, P.-J.;Lee, J.; JRI LEE; Lee, J.; Chen, Y.-L.; Kao, C.; Peng, P.-J. |
| 臺大學術典藏 |
2020-06-11T07:06:12Z |
56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS
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Lee, J.;Chiang, P.-C.;Weng, C.-C.; Lee, J.; Chiang, P.-C.; Weng, C.-C.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:12Z |
A 60-GHz FSK transceiver with automatically-calibrated demodulator in 90-nm CMOS
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Wang, H.;Hung, M.-H.;Yeh, Y.-C.;Lee, J.; Wang, H.; Hung, M.-H.; Yeh, Y.-C.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:11Z |
4?25 Gb/s transceiver with optical front-end for 100 GbE system in 65 nm CMOS technology
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Chiang, P.-C.;Jiang, J.-Y.;Hung, H.-W.;Wu, C.-Y.;Chen, G.-S.;Lee, J.; Chiang, P.-C.; Jiang, J.-Y.; Hung, H.-W.; Wu, C.-Y.; Chen, G.-S.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:11Z |
A 79-GHz bidirectional pulse radar system with injection-regenerative receiver in 65 nm CMOS
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Peng, P.-J.;Kao, C.;Wu, C.-Y.;Lee, J.; Peng, P.-J.; Kao, C.; Wu, C.-Y.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:11Z |
A 94 GHz 3D image radar engine with 4TX/4RX beamforming scan technique in 65 nm CMOS technology
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Peng, P.-J.;Chen, P.-N.;Kao, C.;Chen, Y.-L.;Lee, J.; Peng, P.-J.; Chen, P.-N.; Kao, C.; Chen, Y.-L.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:11Z |
Design of 56 Gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies
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JRI LEE; Lee, J.;Chiang, P.-C.;Peng, P.-J.;Chen, L.-Y.;Weng, C.-C.; Lee, J.; Chiang, P.-C.; Peng, P.-J.; Chen, L.-Y.; Weng, C.-C. |
| 臺大學術典藏 |
2020-06-11T07:06:10Z |
A 2 x 25-Gb/s Receiver With 2:5 DMUX for 100-Gb/s Ethernet
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Wu, Ke-Chung;Lee, Jri; Wu, Ke-Chung; Lee, Jri; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:10Z |
W-Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology
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Huang, Shih-Jou;Yeh, Yu-Ching;Wang, Huaide;Chen, Pang-Ning;Lee, Jri; Huang, Shih-Jou; Yeh, Yu-Ching; Wang, Huaide; Chen, Pang-Ning; Lee, Jri; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:10Z |
A low-power low-cost fully-integrated 60-GHz transceiver system with OOK modulation and on-board antenna assembly
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Lee, J.;Chen, Y.;Huang, Y.; Lee, J.; Chen, Y.; Huang, Y.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:10Z |
A 21-Gb/s 87-mW transceiver with FFE/DFE/analog equalizer in 65-nm CMOS technology
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Wang, H.;Lee, J.; Wang, H.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
Study of Subharmonically Injection-Locked PLLs
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Lee, Jri;Wang, Huaide; Lee, Jri; Wang, Huaide; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
A 75-GHz phase-locked loop in 90-nm CMOS technology
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Lee, J.;Liu, M.;Wang, H.; Lee, J.; Liu, M.; Wang, H.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition
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Lee, Jri;Wu, Ke-Chung; Lee, Jri; Wu, Ke-Chung; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:07Z |
An 87GHz QPSK transceiver with costas-loop carrier recovery in 65nm CMOS
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Huang, S.-J.; Yeh, Y.-C.; Wang, H.; Chen, P.-N.; Lee, J.; JRI LEE; Huang, S.-J.;Yeh, Y.-C.;Wang, H.;Chen, P.-N.;Lee, J. |
| 臺大學術典藏 |
2020-06-11T07:06:07Z |
100Gb/s ethernet chipsets in 65nm CMOS technology
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Jiang, J.-Y.;Chiang, P.-C.;Hung, H.-W.;Lin, C.-L.;Yoon, T.;Lee, J.; Jiang, J.-Y.; Chiang, P.-C.; Hung, H.-W.; Lin, C.-L.; Yoon, T.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:07Z |
A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS
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Chen, P.-N.;Peng, P.-J.;Kao, C.;Chen, Y.-L.;Lee, J.; Chen, P.-N.; Peng, P.-J.; Kao, C.; Chen, Y.-L.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:07Z |
A 40Gb/s TX and RX chip set in 65nm CMOS
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Chen, M.-S.;Shih, Y.-N.;Lin, C.-L.;Hung, H.-W.;Lee, J.; Chen, M.-S.; Shih, Y.-N.; Lin, C.-L.; Hung, H.-W.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:07Z |
60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS
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Chiang, P.-C.;Hung, H.-W.;Chu, H.-Y.;Chen, G.-S.;Lee, J.; Chiang, P.-C.; Hung, H.-W.; Chu, H.-Y.; Chen, G.-S.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:06Z |
A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition
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Lee, J.;Wu, K.-C.; Lee, J.; Wu, K.-C.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:06Z |
A fully integrated 77GHz FMCW radar system in 65nm CMOS
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JRI LEE; Li, Y.-A.;Hung, M.-H.;Huang, S.-J.;Lee, J.; Li, Y.-A.; Hung, M.-H.; Huang, S.-J.; Lee, J. |
| 臺大學術典藏 |
2020-06-11T07:06:06Z |
A low-power fully integrated 60ghz transceiver system with OOK modulation and on-board antenna assembly
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Lee, J.;Huang, Y.;Chen, Y.;Lu, H.;Chang, C.; Lee, J.; Huang, Y.; Chen, Y.; Lu, H.; Chang, C.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:06Z |
A 2x25Gb/s deserializer with 2:5 DMUX for 100Gb/s ethernet applications
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Wu, K.-C.;Lee, J.; Wu, K.-C.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:05Z |
A 20Gb/s Duobinary Transceiver in 90nm CMOS.
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Lee, Jri;Chen, Ming-Shuan;Wang, Huaide; Lee, Jri; Chen, Ming-Shuan; Wang, Huaide; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:05Z |
Subharmonically injection-locked PLLS for ultra-low-noise clock generation
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Lee, J.;Wang, H.;Chen, W.-T.;Lee, Y.-P.; Lee, J.; Wang, H.; Chen, W.-T.; Lee, Y.-P.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:04Z |
Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology
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Chen, G.-S.;Wu, C.-Y.;Lin, C.-L.;Hung, H.-W.;Lee, J.; Chen, G.-S.; Wu, C.-Y.; Lin, C.-L.; Hung, H.-W.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:03Z |
A Fully-Integrated 77GHz phase-array radar system with 1TX/4RX frontend and digital beamforming technique
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Huang, S.-J.;Chen, Y.-L.;Chu, H.-Y.;Chen, P.-N.;Chang, H.-Y.;Kuo, C.-Y.;Kao, C.;Lee, J.; Huang, S.-J.; Chen, Y.-L.; Chu, H.-Y.; Chen, P.-N.; Chang, H.-Y.; Kuo, C.-Y.; Kao, C.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2018-09-10T07:09:37Z |
mm-Wave Silicon Technology: 60GHz and Beyond (Chapter 5: Voltage-Controlled Oscillators and Frequency Dividers)
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Jri Lee; Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T07:09:37Z |
mm-Wave Silicon Technology: 60GHz and Beyond (Chapter 5: Voltage-Controlled Oscillators and Frequency Dividers)
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Jri Lee; Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T07:09:37Z |
mm-Wave Silicon Technology: 60GHz and Beyond (Chapter 5: Voltage-Controlled Oscillators and Frequency Dividers)
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Jri Lee; Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T07:09:37Z |
Efficient frequency conversion apparatus for use with nultimode solid-state lasers
|
rew Kung; Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T07:09:37Z |
Efficient frequency conversion apparatus for use with nultimode solid-state lasers
|
rew Kung; Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
A 75GHz PLL in 90nmCMOS
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Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
A 75GHz PLL in 90nmCMOS
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Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
A 20Gb/s broadband transmitter with auto-configuration technique
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Jri Lee; Huaide Wang; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
A 20Gb/s broadband transmitter with auto-configuration technique
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Jri Lee; Huaide Wang; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
High-speed clock and data recovery circuit
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Jri Lee; Behzad Razavi; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
High-speed clock and data recovery circuit
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Jri Lee; Behzad Razavi; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:03:22Z |
A 20-Gb/s Adaptive Equalizer in 0.13 μm CMOS Technology
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Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:03:22Z |
A 20-Gb/s Adaptive Equalizer in 0.13 μm CMOS Technology
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Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:03:21Z |
High-Speed Circuit Designs for Transmitters in Broadband Data Links
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Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:03:21Z |
High-Speed Circuit Designs for Transmitters in Broadband Data Links
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Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T05:29:28Z |
Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS Technology
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Jri Lee; Shanghann Wu; JRI LEE |
| 臺大學術典藏 |
2018-09-10T05:29:28Z |
Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS Technology
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Jri Lee; Shanghann Wu; JRI LEE |
| 臺大學術典藏 |
2018-09-10T04:36:05Z |
Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits
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Jri Lee; Ken Kundert; Behzad Razavi; JRI LEE |
| 臺大學術典藏 |
2018-09-10T04:36:05Z |
Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits
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Jri Lee; Ken Kundert; Behzad Razavi; JRI LEE |
| 臺大學術典藏 |
2010 |
A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology
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Lee, Jri;Li, Yi-An;Hung, Meng-Hsiung;Huang, Shih-Jou; Lee, Jri; Li, Yi-An; Hung, Meng-Hsiung; Huang, Shih-Jou; JRI LEE |
顯示項目 1-48 / 48 (共1頁)
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