| 臺大學術典藏 |
2020-06-11T07:06:06Z |
A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition
|
Lee, J.;Wu, K.-C.; Lee, J.; Wu, K.-C.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:06Z |
A fully integrated 77GHz FMCW radar system in 65nm CMOS
|
JRI LEE; Li, Y.-A.;Hung, M.-H.;Huang, S.-J.;Lee, J.; Li, Y.-A.; Hung, M.-H.; Huang, S.-J.; Lee, J. |
| 臺大學術典藏 |
2020-06-11T07:06:06Z |
A low-power fully integrated 60ghz transceiver system with OOK modulation and on-board antenna assembly
|
Lee, J.;Huang, Y.;Chen, Y.;Lu, H.;Chang, C.; Lee, J.; Huang, Y.; Chen, Y.; Lu, H.; Chang, C.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:06Z |
A 2x25Gb/s deserializer with 2:5 DMUX for 100Gb/s ethernet applications
|
Wu, K.-C.;Lee, J.; Wu, K.-C.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:05Z |
A 20Gb/s Duobinary Transceiver in 90nm CMOS.
|
Lee, Jri;Chen, Ming-Shuan;Wang, Huaide; Lee, Jri; Chen, Ming-Shuan; Wang, Huaide; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:05Z |
Subharmonically injection-locked PLLS for ultra-low-noise clock generation
|
Lee, J.;Wang, H.;Chen, W.-T.;Lee, Y.-P.; Lee, J.; Wang, H.; Chen, W.-T.; Lee, Y.-P.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:04Z |
Fully-integrated 40-Gb/s pulse pattern generator and bit-error-rate tester chipsets in 65-nm CMOS technology
|
Chen, G.-S.;Wu, C.-Y.;Lin, C.-L.;Hung, H.-W.;Lee, J.; Chen, G.-S.; Wu, C.-Y.; Lin, C.-L.; Hung, H.-W.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:03Z |
A Fully-Integrated 77GHz phase-array radar system with 1TX/4RX frontend and digital beamforming technique
|
Huang, S.-J.;Chen, Y.-L.;Chu, H.-Y.;Chen, P.-N.;Chang, H.-Y.;Kuo, C.-Y.;Kao, C.;Lee, J.; Huang, S.-J.; Chen, Y.-L.; Chu, H.-Y.; Chen, P.-N.; Chang, H.-Y.; Kuo, C.-Y.; Kao, C.; Lee, J.; JRI LEE |
| 臺大學術典藏 |
2018-09-10T07:09:37Z |
mm-Wave Silicon Technology: 60GHz and Beyond (Chapter 5: Voltage-Controlled Oscillators and Frequency Dividers)
|
Jri Lee; Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T07:09:37Z |
mm-Wave Silicon Technology: 60GHz and Beyond (Chapter 5: Voltage-Controlled Oscillators and Frequency Dividers)
|
Jri Lee; Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T07:09:37Z |
mm-Wave Silicon Technology: 60GHz and Beyond (Chapter 5: Voltage-Controlled Oscillators and Frequency Dividers)
|
Jri Lee; Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T07:09:37Z |
Efficient frequency conversion apparatus for use with nultimode solid-state lasers
|
rew Kung; Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T07:09:37Z |
Efficient frequency conversion apparatus for use with nultimode solid-state lasers
|
rew Kung; Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
A 75GHz PLL in 90nmCMOS
|
Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
A 75GHz PLL in 90nmCMOS
|
Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
A 20Gb/s broadband transmitter with auto-configuration technique
|
Jri Lee; Huaide Wang; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
A 20Gb/s broadband transmitter with auto-configuration technique
|
Jri Lee; Huaide Wang; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
High-speed clock and data recovery circuit
|
Jri Lee; Behzad Razavi; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:37:57Z |
High-speed clock and data recovery circuit
|
Jri Lee; Behzad Razavi; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:03:22Z |
A 20-Gb/s Adaptive Equalizer in 0.13 μm CMOS Technology
|
Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:03:22Z |
A 20-Gb/s Adaptive Equalizer in 0.13 μm CMOS Technology
|
Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:03:21Z |
High-Speed Circuit Designs for Transmitters in Broadband Data Links
|
Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T06:03:21Z |
High-Speed Circuit Designs for Transmitters in Broadband Data Links
|
Jri Lee; JRI LEE |
| 臺大學術典藏 |
2018-09-10T05:29:28Z |
Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS Technology
|
Jri Lee; Shanghann Wu; JRI LEE |
| 臺大學術典藏 |
2018-09-10T05:29:28Z |
Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-μm CMOS Technology
|
Jri Lee; Shanghann Wu; JRI LEE |
| 臺大學術典藏 |
2018-09-10T04:36:05Z |
Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits
|
Jri Lee; Ken Kundert; Behzad Razavi; JRI LEE |
| 臺大學術典藏 |
2018-09-10T04:36:05Z |
Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits
|
Jri Lee; Ken Kundert; Behzad Razavi; JRI LEE |
| 臺大學術典藏 |
2010 |
A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology
|
Lee, Jri;Li, Yi-An;Hung, Meng-Hsiung;Huang, Shih-Jou; Lee, Jri; Li, Yi-An; Hung, Meng-Hsiung; Huang, Shih-Jou; JRI LEE |
