臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

About TAIR
	About TAIR

Browse By
	Institution
	Author
	Title
	Date
	Statistics Chart
	Institution Facts
	Trend

News
	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

Copyright
	Publisher & Journal Policy
	TAIR Copyright Conference Minutes

Related Links
	機構典藏計畫網站
	ROAR
	OpenDOAR
	SHERPA
	OAIster
	JAIRO
	Ira
	DSPACE
	RWWR
	臺大學術典藏NTU Scholars

"jung lin yang"

Return to Browse by Author
Sorting by Title	Sort by Date

Showing items 1-24 of 24 (1 Page(s) Totally)
1
View [10|25|50] records per page

Institution	Date	Title	Author
南台科技大學	2022-09	基於物件偵測的咖啡瑕疵豆辨識技術	Wei-Che Chung;Jung-Lin Yang
南台科技大學	2020-07	微電腦介面技術翻轉教學策略實踐研究	楊榮林;Jung-Lin Yang
南台科技大學	2010-05	微型自我時序微處理機-基於FPGA 的非同步電路設計實例	盧欣農; 楊榮林; 尤偉霖; 陳三霖; Shin-Nung Lu; Jung-Lin Yang; Wei-Lin Yu; San-Lin Chen
南台科技大學	2007	REMOVAL OF RESETTING TRANSITIONS FOR ASYNCHRONOUS FSM	Jung-Lin Yang; Chih-Feng Tai; Wei-Che Hsu
南台科技大學	2007	64-Bit High-Speed Asynchronous Comparator	Jung-Lin Yang; Wei-Peng Teng; Sung-Min Lin
南台科技大學	2007	Post-Chip Adjustable Low Power Delay Element	Jung-Lin Yang; Chih-Wei Chao; 楊榮林;趙智偉
南台科技大學	2006-12	Adjustable Extremely Low Power Delay Line	Jung-Lin Yang; Chih-Wei Chao; Sung-Min Lin
南台科技大學	2006-11	High-Level Synthesis for Self-Timed Systems	Jung-Lin Yang; Hsu-Ching Tien; Chia-Ming Hsu; Sung-Min Lin; 楊榮林;田旭清;許家銘;林嵩閔
南台科技大學	2006-11	Swift Transition Weight Analysis for Asynchronous Finite State	Jung-Lin Yang; Chih-Feng Tai; Sung-Min Lin
南台科技大學	2006-11	Tunable Delay Element for Low Power VLSI Circuit Design	Jung-Lin Yang; Chih-Wei Chao; Sung-Min Lin
南台科技大學	2006-11	Technology-Independent Synthesis for Channel-Level Asynchronous System,	Jung-Lin Yang; Hsu-Ching Tien
南台科技大學	2006-11	Channel-Level Synthesis for Asynchronous Circuit Design	Jung-Lin Yang; Hsu-Ching Tien
南台科技大學	2006-08	Improved Technique on Parallelism for Asynchronous Controllers	Jung-Lin Yang; Erik Brunvand
南台科技大學	2006-05	High-Level Synthesis for Self-Timed Systems	Hsu-Ching Tien; Jung-Lin Yang
南台科技大學	2006-03	非同步VLSI設計通道層描述簡介	楊榮林; Jung-Lin Yang
南台科技大學	2005-12	Self-Timed Circuits Using Single-Rail DCVSL Template	Jung-Lin Yang; Erik Brunvand
南台科技大學	2005-12	HDL Modeling for Optimization and Verification of Asynchronous Controllers	Jung-Lin Yang; Erik Brunvand; Sung-Min Lin
南台科技大學	2005-08	Pseudo Dynamic DCVSL Template For Power-Conservative Design	Jung-Lin Yang; Erik Brunvand
南台科技大學	2005-08	HDL Modeling for Optimization and Verification Of Extended Burst-Mode	Jung-Lin Yang; Erik Brunvand; Sung-Min Lin
南台科技大學	2005-08	An Asymmetrical Low-Power Tunable Delay Element	Jung-Lin Yang; Wen-Yueh Lai; Chen-Chia Yang
南台科技大學	2005-05	HDL Modeling for Burst-mode and Extended Burst-mode (BM/XBM) Asynchronous Controllers	Jung-Lin Yang; Sung-Min Lin
南台科技大學	2005-05	Programmable Generalized C-Element Structure	Wen-Yueh Lai; Jung-Lin Yang
南台科技大學	2003-05	Using Dynamic Domino Circuits in Self-Timed Systems	Jung-Lin Yang; Erik Brunvand; 楊榮林
南台科技大學	2003	Self-Timed Design with Dynamic Domino Circuits	Jung-Lin Yang; Erik Brunvand

Showing items 1-24 of 24 (1 Page(s) Totally)
1
View [10|25|50] records per page

	English \| 正體中文 \| 简体中文 \| Total items :2815453
	Visitors : 27429101 Online Users : 582 Project Commissioned by the Ministry of Education Project Executed by National Taiwan University Library