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Institution	Date	Title	Author
臺大學術典藏	2019-10-31T07:45:04Z	A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip	CHIA-HSIANG YANG;K.-T. Tang;M.-F. Chang;C.-C. Hsieh;H. Chen;H. Chiueh;C.-H. Yang;G. Wang;S.-W. Chiu;J.-Y. Jhang;K.-H. Chang;T.-I Chou; T.-I Chou; K.-H. Chang; J.-Y. Jhang; S.-W. Chiu; G. Wang; C.-H. Yang; H. Chiueh; H. Chen; C.-C. Hsieh; M.-F. Chang; K.-T. Tang; CHIA-HSIANG YANG
臺大學術典藏	2019-10-31T06:58:45Z	Path Controllability Analysis for High Quality Designs	SY-YEN KUO;C. Huang;S. Y. Kuo;K. H. Chang;H. Z. Chou;L. J. Chen; L. J. Chen; H. Z. Chou; K. H. Chang; S. Y. Kuo; C. Huang; SY-YEN KUO
臺大學術典藏	2018-09-10T15:36:26Z	Handling Nondeterminism in Logic Simulation So That Your Waveform Can Be Trusted Again	H. Z. Chou;K. H. Chang;S. Y. Kuo; H. Z. Chou; K. H. Chang; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T09:24:51Z	Effectiveness of External Respiratory Surrogates for in vivo Liver Motion Estimation	K. H. Chang;M. C. Ho;C. C. Yeh;Y. C. Chen;F. L. Lian;W. L. Lin;J. Y. Yen;Y. Y. Chen; K. H. Chang; M. C. Ho; C. C. Yeh; Y. C. Chen; F. L. Lian; W. L. Lin; J. Y. Yen; Y. Y. Chen; FENG-LI LIAN; YUNG-YAW CHEN; CHI-CHUAN YEH; JIA-YUSH YEN
臺大學術典藏	2018-09-10T09:24:51Z	Respiration Induced Liver Motion Tracking Control For High Intensity Focused Ultrasound Treatment	K. T. Teng;K. H. Chang;Y. Y. Chen;T. C. Tsao; K. T. Teng; K. H. Chang; Y. Y. Chen; T. C. Tsao; YUNG-YAW CHEN
臺大學術典藏	2018-09-10T09:24:51Z	Improvement on the Thickness-direction Resolution of 2D US Image Positioning	Z. H. Li;K. H. Chang;T. C. Chen;M. C. Ho;F. L. Lian;J. Y. Yen;W. L. Lin;Y. Y. Chen; Z. H. Li; K. H. Chang; T. C. Chen; M. C. Ho; F. L. Lian; J. Y. Yen; W. L. Lin; Y. Y. Chen; YUNG-YAW CHEN
臺大學術典藏	2018-09-10T09:24:51Z	Synchronized Tracking of Respiration-Induced Liver Tumor Motion by Ultrasound Imaging	M. H. Tsai;K. H. Chang;M. C. Ko;M. C. Ho;F. L. Lian;J. Y. Yen;W. L. Lin;Y. Y. Chen; M. H. Tsai; K. H. Chang; M. C. Ko; M. C. Ho; F. L. Lian; J. Y. Yen; W. L. Lin; Y. Y. Chen; YUNG-YAW CHEN
臺大學術典藏	2018-09-10T08:46:24Z	Applying Verification Intention for Design Customization via Property Mining under Constrained Testbenches	C. N. Chung; C. W. Chang; K. H. Chang; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T08:46:23Z	Formal Reset Recovery Slack Calculation at the Register Transfer Level	C. N. Chung; C. W. Chang; K. H. Chang; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T08:46:22Z	Facilitating Unreachable Code Diagnosis and Debugging	H. Z. Chou; K. H. Chang; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T08:18:12Z	Finding Reset Nondeterminism in RTL Designs–Scalable X-Analysis Methodology and Case Study	H. Z. Chou;H. Yu;K. H. Chang;D. Dobbyn;S. Y. Kuo; H. Z. Chou; H. Yu; K. H. Chang; D. Dobbyn; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T08:18:12Z	Automatic Constraint Generation for Software-Based Post-Silicon Bug Repair	H. Z. Chou;K. H. Chang;S. Y. Kuo; H. Z. Chou; K. H. Chang; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T08:18:12Z	Automating Unreachable Code Diagnosis and Debugging	H. Z. Chou;K. H. Chang;S. Y. Kuo; H. Z. Chou; K. H. Chang; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T08:18:11Z	Accurately Handle Don’t-Care Conditions in High-Level Designs and Application for Reducing Initialized Registers	H. Z. Chou;K. H. Chang;S. Y. Kuo; H. Z. Chou; K. H. Chang; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T08:18:11Z	Optimizing Blocks in an SoC Using Symbolic Code-Statement Reachability Analysis	H. Z. Chou;K. H. Chang;S. Y. Kuo; H. Z. Chou; K. H. Chang; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T07:41:50Z	Enhancing Bug Hunting Using High-Level Symbolic Simulation	H. Z. Chou;I. H. Lin;C. S. Yang;K. H. Chang;S. Y. Kuo; H. Z. Chou; I. H. Lin; C. S. Yang; K. H. Chang; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T07:41:49Z	Handling Don't-Care Conditions in High-LevelSynthesis and Application for Reducing Initialized Registers	H. Z. Chou;K. H. Chang;S. Y. Kuo; H. Z. Chou; K. H. Chang; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T07:08:23Z	Efficiency on Snake Robot Locomotion with Constant and Variable Bending Angles	K. H. Chang; Y. Y. Chen; YUNG-YAW CHEN
臺大學術典藏	2018-09-10T05:26:57Z	Automatic Partitioner for Behavior Level Distributed Logic Simulation	K. H. Chang; J. Y. Kang; H. W. Wang; W. T. Tu; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:59:13Z	Techniques to Reduce Synchronization in Distributed Parallel Logic Simulation	K. H. Chang; W. T. Tu; H. W. Wang; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:59:12Z	A Temporal Assertion Extension to Verilog	K. H. Chang; W. T. Tu; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:59:10Z	Automatic Partitioner for Distributed Parallel Logic Simulation	K. H. Chang; H. W. Wang; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:59:10Z	System Level Assertion-Based Verification Environment for PCI/PCI-X and PCI-Express	C. C; Yu; K. H. Chang; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:35:24Z	A PCI-X Verification Environment Using C and Verilog	K. H. Chang; Y. C. Su; W. T. Tu; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO
臺大學術典藏	2018-09-10T04:35:24Z	A Tag-Augmented Temporal Logic Checker	K. H. Chang; W. T. Tu; Y. J. Yeh; S. Y. Kuo; SY-YEN KUO

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