臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	Repositories
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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
國立交通大學	2014-12-12T02:13:06Z	晶圓製造廠生產規劃模式之構建	李國禎; K. J. Lee; 鍾淑馨; S. H. Chung
義守大學	2009-07	Tribological behavior of carbon nanotube/aluminosilicate composites prepared through TEOS/boehmite catalyst sol–gel and CVD process	K.J. Lee;Y.T. Yeh;H.Z. Cheng;P.C. Chang;S.W. Lin;Y.D. Chen
元智大學	2009-04	Refinement of circular-polarization based on multilayer film structure	周錫增; B. Li; K-J Lee; S-H Huang; W-Y Gu
元智大學	2008-11	A POLARIZATION COMPENSATION APPROACH UTILIZING A PARABOLOID PHOTONIC-CRYSTAL STRUCTURE FOR CROSSED-DIPOLE EXCITED REFLECTOR ANTENNAS	周錫增; B. Li; K.-J. Lee; W. Gu
元智大學	2007-08	One-Dimensional Photonic Crystals based on Polarization Compensation Approach	周錫增; K-J Lee; B. Li; G-L Hong; Y-W Yin
元智大學	2007-08	One-Dimensional Photonic Crystals based on Polarization Compensation Approach	周錫增; K-J Lee; B. Li; G-L Hong; Y-W Yin
義守大學	2007-04	The influence of carbon fiber orientation on the mechanical and tribological behavior of carbon fiber/LCP composites	K.J. Lee;H.Z. Cheng;W.S. Jou;G.J. Chen;C.W. Liang; 李國榮
義守大學	2003-02	Microstructure study of PAN-pitch carbon-carbon composite lubricative film	K.J Lee;J.H Chern Lin;C.P Ju
義守大學	2000-05	Multi-braking tribological behavior of PAN-pitch, PAN-CVI, and pitch-resin-CVI carbon-carbon compsites	C.P Ju;J.H Chern Lin;K.J Lee;H.H Kuo
南台科技大學	1998-12	Determination of threshold voltage for CMOS gates to facilitate test pattern generation and fault simulation	K. J. Lee; J. J. Tang
南台科技大學	1998-12	On the determination of threshold voltages for CMOS gate to facilitate test pattern generation and fault simulation	K. J. Lee; J. J. Tang
南台科技大學	1998-10	A new representation for programmable logic arrays to facilitate testing and logic design	J. J. Tang; K. J. Lee; B. D. Liu;唐經洲; Jing-Jou Tang
南台科技大學	1996-01	Two modeling techniques for CMOS Circuits to enhance test generation and fault simulation for bridging faults	K. J. Lee; J. J. Tang; 唐經洲
南台科技大學	1995-05	An IDDQ fault model to facilitate the design of built-in current sensor (BICSs)	B. D. Liu; J. J. Tang; K. J. Lee
南台科技大學	1994-08	Bulit-in intermediate voltage testing for CMOS circuits	K. J. Lee; J. J. Tang
南台科技大學	1994-01	Physical fault consideration of test pattern generation for large embeeded PLAs	B. D. Liu; J. J. Tang; K. J. Lee
南台科技大學	1993-09	A real time IDDQ testing scheme using current conveyor technique	J. J. Tang; K.J. Lee; B.D. Liu
南台科技大學	1993-09	Maximal fault diagnosis resolution for programmable logic array	B. D. Liu; J. J. Tang; K. J. Lee
南台科技大學	1993-08	A new current sensing technique for IDDQ testing	J. J. Tang; K. J. Lee; B. D. Liu

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