臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Showing items 11-19 of 19 (1 Page(s) Totally)
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Institution	Date	Title	Author
南台科技大學	1998-12	On the determination of threshold voltages for CMOS gate to facilitate test pattern generation and fault simulation	K. J. Lee; J. J. Tang
南台科技大學	1998-10	A new representation for programmable logic arrays to facilitate testing and logic design	J. J. Tang; K. J. Lee; B. D. Liu;唐經洲; Jing-Jou Tang
南台科技大學	1996-01	Two modeling techniques for CMOS Circuits to enhance test generation and fault simulation for bridging faults	K. J. Lee; J. J. Tang; 唐經洲
南台科技大學	1995-05	An IDDQ fault model to facilitate the design of built-in current sensor (BICSs)	B. D. Liu; J. J. Tang; K. J. Lee
南台科技大學	1994-08	Bulit-in intermediate voltage testing for CMOS circuits	K. J. Lee; J. J. Tang
南台科技大學	1994-01	Physical fault consideration of test pattern generation for large embeeded PLAs	B. D. Liu; J. J. Tang; K. J. Lee
南台科技大學	1993-09	A real time IDDQ testing scheme using current conveyor technique	J. J. Tang; K.J. Lee; B.D. Liu
南台科技大學	1993-09	Maximal fault diagnosis resolution for programmable logic array	B. D. Liu; J. J. Tang; K. J. Lee
南台科技大學	1993-08	A new current sensing technique for IDDQ testing	J. J. Tang; K. J. Lee; B. D. Liu

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