|
|
Taiwan Academic Institutional Repository >
Browse by Author
|
"ker md"
Showing items 1-25 of 129 (6 Page(s) Totally)
1 2 3 4 5 6 > >>
View [10|25|50] records per page
| 國立交通大學 |
2019-04-02T06:04:42Z |
Active device under bond pad to save I/O layout for high-pin-count SOC
|
Ker, MD; Peng, JJ; Jiang, HC |
| 國立交通大學 |
2019-04-02T05:58:32Z |
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
|
Ker, MD; Wu, CY; Cheng, T; Chang, HH |
| 國立交通大學 |
2014-12-08T15:49:03Z |
Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area
|
Ker, MD; Wu, CY; Huang, CC; Chen, TY |
| 國立交通大學 |
2014-12-08T15:48:43Z |
Improved output ESD protection by dynamic gate floating design
|
Chang, HH; Ker, MD |
| 國立交通大學 |
2014-12-08T15:46:57Z |
Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology
|
Chang, HH; Ker, MD; Wu, JC |
| 國立交通大學 |
2014-12-08T15:46:47Z |
New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness
|
Ker, MD; Chen, TY; Chang, HH |
| 國立交通大學 |
2014-12-08T15:45:35Z |
Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
|
Ker, MD; Chang, HH |
| 國立交通大學 |
2014-12-08T15:45:27Z |
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
|
Ker, MD; Lo, WY |
| 國立交通大學 |
2014-12-08T15:44:57Z |
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications
|
Ker, MD; Chen, TY; Wu, CY; Chang, HH |
| 國立交通大學 |
2014-12-08T15:44:09Z |
Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard
|
Ker, MD; Sung, YY |
| 國立交通大學 |
2014-12-08T15:43:58Z |
On-chip ESD protection design by using polysilicon diodes in CMOS process
|
Ker, MD; Chen, TY; Wang, TH; Wu, CY |
| 國立交通大學 |
2014-12-08T15:43:10Z |
Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology
|
Ker, MD; Jiang, HC; Chang, CY |
| 國立交通大學 |
2014-12-08T15:43:05Z |
Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit
|
Ker, MD; Chen, TY |
| 國立交通大學 |
2014-12-08T15:42:25Z |
Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits
|
Ker, MD; Chen, TY; Wu, CY |
| 國立交通大學 |
2014-12-08T15:42:23Z |
Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
|
Ker, MD; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:42:20Z |
Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs
|
Ker, MD; Peng, JJ |
| 國立交通大學 |
2014-12-08T15:42:19Z |
ESD protection design for CMOS RF integrated circuits using polysilicon diodes
|
Ker, MD; Chang, CY |
| 國立交通大學 |
2014-12-08T15:42:10Z |
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
|
Ker, MD; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:41:59Z |
Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog applications
|
Ker, MD; Chen, TY; Wu, CY |
| 國立交通大學 |
2014-12-08T15:41:45Z |
Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology
|
Ker, MD; Hsu, HC; Peng, JJ |
| 國立交通大學 |
2014-12-08T15:41:20Z |
Substrate-triggered ESD protection circuit without extra process modification
|
Ker, MD; Chen, TY |
| 國立交通大學 |
2014-12-08T15:41:19Z |
Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
|
Ker, MD; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:41:07Z |
Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process
|
Ker, MD; Chen, TY |
| 國立交通大學 |
2014-12-08T15:40:59Z |
Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology
|
Ker, MD; Lo, WY |
| 國立交通大學 |
2014-12-08T15:40:49Z |
CMOS chip as luminescent sensor for biochemical reactions
|
Lu, U; Hu, BCP; Shih, YC; Yang, YS; Wu, CY; Yuan, CJ; Ker, MD; Wu, TK; Li, YK; Hsieh, YZ; Hsu, WY; Lin, CT |
Showing items 1-25 of 129 (6 Page(s) Totally)
1 2 3 4 5 6 > >>
View [10|25|50] records per page
|
