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Showing items 1-10 of 129 (13 Page(s) Totally)
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| 國立交通大學 |
2019-04-02T06:04:42Z |
Active device under bond pad to save I/O layout for high-pin-count SOC
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Ker, MD; Peng, JJ; Jiang, HC |
| 國立交通大學 |
2019-04-02T05:58:32Z |
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
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Ker, MD; Wu, CY; Cheng, T; Chang, HH |
| 國立交通大學 |
2014-12-08T15:49:03Z |
Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area
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Ker, MD; Wu, CY; Huang, CC; Chen, TY |
| 國立交通大學 |
2014-12-08T15:48:43Z |
Improved output ESD protection by dynamic gate floating design
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Chang, HH; Ker, MD |
| 國立交通大學 |
2014-12-08T15:46:57Z |
Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology
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Chang, HH; Ker, MD; Wu, JC |
| 國立交通大學 |
2014-12-08T15:46:47Z |
New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness
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Ker, MD; Chen, TY; Chang, HH |
| 國立交通大學 |
2014-12-08T15:45:35Z |
Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
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Ker, MD; Chang, HH |
| 國立交通大學 |
2014-12-08T15:45:27Z |
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
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Ker, MD; Lo, WY |
| 國立交通大學 |
2014-12-08T15:44:57Z |
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications
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Ker, MD; Chen, TY; Wu, CY; Chang, HH |
| 國立交通大學 |
2014-12-08T15:44:09Z |
Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard
|
Ker, MD; Sung, YY |
Showing items 1-10 of 129 (13 Page(s) Totally)
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