臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
國立交通大學	2019-04-02T06:04:42Z	Active device under bond pad to save I/O layout for high-pin-count SOC	Ker, MD; Peng, JJ; Jiang, HC
國立交通大學	2019-04-02T05:58:32Z	Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC	Ker, MD; Wu, CY; Cheng, T; Chang, HH
國立交通大學	2014-12-08T15:49:03Z	Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area	Ker, MD; Wu, CY; Huang, CC; Chen, TY
國立交通大學	2014-12-08T15:48:43Z	Improved output ESD protection by dynamic gate floating design	Chang, HH; Ker, MD
國立交通大學	2014-12-08T15:46:57Z	Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology	Chang, HH; Ker, MD; Wu, JC
國立交通大學	2014-12-08T15:46:47Z	New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness	Ker, MD; Chen, TY; Chang, HH
國立交通大學	2014-12-08T15:45:35Z	Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger	Ker, MD; Chang, HH
國立交通大學	2014-12-08T15:45:27Z	Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process	Ker, MD; Lo, WY
國立交通大學	2014-12-08T15:44:57Z	ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications	Ker, MD; Chen, TY; Wu, CY; Chang, HH
國立交通大學	2014-12-08T15:44:09Z	Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard	Ker, MD; Sung, YY
國立交通大學	2014-12-08T15:43:58Z	On-chip ESD protection design by using polysilicon diodes in CMOS process	Ker, MD; Chen, TY; Wang, TH; Wu, CY
國立交通大學	2014-12-08T15:43:10Z	Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology	Ker, MD; Jiang, HC; Chang, CY
國立交通大學	2014-12-08T15:43:05Z	Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit	Ker, MD; Chen, TY
國立交通大學	2014-12-08T15:42:25Z	Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits	Ker, MD; Chen, TY; Wu, CY
國立交通大學	2014-12-08T15:42:23Z	Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface	Ker, MD; Chuang, CH
國立交通大學	2014-12-08T15:42:20Z	Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs	Ker, MD; Peng, JJ
國立交通大學	2014-12-08T15:42:19Z	ESD protection design for CMOS RF integrated circuits using polysilicon diodes	Ker, MD; Chang, CY
國立交通大學	2014-12-08T15:42:10Z	Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers	Ker, MD; Chuang, CH
國立交通大學	2014-12-08T15:41:59Z	Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog applications	Ker, MD; Chen, TY; Wu, CY
國立交通大學	2014-12-08T15:41:45Z	Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology	Ker, MD; Hsu, HC; Peng, JJ
國立交通大學	2014-12-08T15:41:20Z	Substrate-triggered ESD protection circuit without extra process modification	Ker, MD; Chen, TY
國立交通大學	2014-12-08T15:41:19Z	Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process	Ker, MD; Hsu, KC
國立交通大學	2014-12-08T15:41:07Z	Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process	Ker, MD; Chen, TY
國立交通大學	2014-12-08T15:40:59Z	Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology	Ker, MD; Lo, WY
國立交通大學	2014-12-08T15:40:49Z	CMOS chip as luminescent sensor for biochemical reactions	Lu, U; Hu, BCP; Shih, YC; Yang, YS; Wu, CY; Yuan, CJ; Ker, MD; Wu, TK; Li, YK; Hsieh, YZ; Hsu, WY; Lin, CT
國立交通大學	2014-12-08T15:40:48Z	High-current characterization of polysilicon diode for electrostatic discharge protection in sub-quarter-micron complementary metal oxide semiconductor technology	Ker, MD; Chang, CY
國立交通大學	2014-12-08T15:40:33Z	Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product	Lin, IC; Huang, CY; Chao, CJ; Ker, MD
國立交通大學	2014-12-08T15:40:32Z	Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process	Chen, TY; Ker, MD
國立交通大學	2014-12-08T15:40:31Z	Latchup-free ESD protection design with complementary substrate-triggered SCR devices	Ker, MD; Hsu, KC
國立交通大學	2014-12-08T15:40:26Z	Analysis and prevention on NC-ball induced ESD damages in a 683-pin BGA packaged chipset IC	Lo, WY; Ker, MD
國立交通大學	2014-12-08T15:40:21Z	SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes	Ker, MD; Hsu, KC
國立交通大學	2014-12-08T15:40:18Z	ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness	Ker, MD; Hsu, HC; Peng, JJ
國立交通大學	2014-12-08T15:40:07Z	Dummy-gate structure to improve turn-on speed of silicon-controlled rectifier (SCR) device for effective electrostatic discharge (ESD) protection	Ker, MD; Hsu, KC
國立交通大學	2014-12-08T15:39:45Z	Active electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) process	Ker, MD; Tseng, TK
國立交通大學	2014-12-08T15:39:41Z	Design optimization of ESD protection and latchup prevention for a serial I/O IC	Huang, CY; Chen, WF; Chuan, SY; Chiu, FC; Tseng, JC; Lin, IC; Chao, CJ; Leu, LY; Ker, MD
國立交通大學	2014-12-08T15:39:34Z	Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing nonconnected balls	Lo, WY; Ker, MD
國立交通大學	2014-12-08T15:38:45Z	Design on ESD protection scheme for IC with power-down-mode operation	Ker, MD; Lin, KH
國立交通大學	2014-12-08T15:38:39Z	Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications	Ker, MD; Peng, JH
國立交通大學	2014-12-08T15:38:37Z	Double snapback characte'ristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design	Ker, MD; Lin, KH
國立交通大學	2014-12-08T15:38:36Z	ESD protection design to overcome internal damage on interface circuits,of a CMOS IC with multiple separated power pins	Ker, MD; Chang, CY; Chang, YS
國立交通大學	2014-12-08T15:38:30Z	On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process	Ker, MD; Lin, KH; Chuang, CH
國立交通大學	2014-12-08T15:38:26Z	SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-mu m fully salicided CMOS process	Ker, MD; Chen, ZP
國立交通大學	2014-12-08T15:36:14Z	ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit	Ker, MD; Hsu, HC
國立交通大學	2014-12-08T15:34:04Z	Decreasing-size distributed ESD protection scheme for broad-band RF circuits	Ker, MD; Kuo, BJ
國立交通大學	2014-12-08T15:27:53Z	AN ON-CHIP ESD PROTECTION CIRCUIT WITH COMPLEMENTARY SCR STRUCTURES FOR SUBMICRON CMOS ICS	KER, MD; WU, CY; JIANG, HC; LEE, CY; KO, J; HSUE, P
國立交通大學	2014-12-08T15:27:47Z	Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's	KER, MD; WU, CY; CHANG, HH; CHENG, T; WU, TS
國立交通大學	2014-12-08T15:27:44Z	Efficient layout style of cmos output buffer to improve driving capability of low-voltage submicron cmos IC's	Ker, MD; Wu, CY; Cheng, T; Chang, HH; Wu, MJN; Yu, TL
國立交通大學	2014-12-08T15:27:17Z	Novel input ESD protection circuit with substrate-triggering technique in a 0.25-mu m shallow-trench-isolation CMOS technology	Ker, MD; Chen, TY; Wu, CY; Tang, H; Su, KC; Sun, SW
國立交通大學	2014-12-08T15:27:06Z	Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits	Ker, MD; Jiang, HC; Chang, CY
國立交通大學	2014-12-08T15:27:05Z	Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications	Ker, MD; Chen, TY; Wu, CY; Chang, HH

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