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Showing items 101-125 of 129 (6 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:19:40Z |
MOS-bounded diodes for on-chip ESD protection in deep submicron CMOS process
|
Ker, MD; Lin, KH; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:19:14Z |
SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology
|
Ker, MD; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:19:14Z |
ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technology
|
Ker, MD; Chuang, CH; Lo, WY |
| 國立交通大學 |
2014-12-08T15:18:55Z |
Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
|
Ker, MD; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:18:48Z |
A new Schmitt trigger circuit in a 0.13-mu m 1/2.5-V CMOS process to receive 3.3-V input signals
|
Chen, SL; Ker, MD |
| 國立交通大學 |
2014-12-08T15:18:41Z |
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
|
Ker, MD; Lin, KH |
| 國立交通大學 |
2014-12-08T15:18:40Z |
Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test
|
Ker, MD; Hsu, SF |
| 國立交通大學 |
2014-12-08T15:18:35Z |
ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS
|
Ker, MD; Chang, WJ |
| 國立交通大學 |
2014-12-08T15:18:35Z |
Investigation on seal-ring rules for IC product reliability in 0.25-mu m CMOS technology
|
Chen, SH; Ker, MD |
| 國立交通大學 |
2014-12-08T15:18:29Z |
ESD protection design for 1-to 10-GHz distributed amplifier in CMOS technology
|
Ker, MD; Hsiao, YW; Kuo, BJ |
| 國立交通大學 |
2014-12-08T15:18:29Z |
Native-NMOS-triggered SCR With faster turn-on speed for effective ESD protection in a 0.13-mu m CMOS process
|
Ker, MD; Hsu, KC |
| 國立交通大學 |
2014-12-08T15:18:07Z |
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
|
Ker, MD; Lin, KH |
| 國立交通大學 |
2014-12-08T15:17:31Z |
Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test
|
Ker, MD; Hsu, SF |
| 國立交通大學 |
2014-12-08T15:17:31Z |
Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board
|
Lin, KH; Ker, MD |
| 國立交通大學 |
2014-12-08T15:17:27Z |
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations
|
Ker, MD; Lin, KH |
| 國立交通大學 |
2014-12-08T15:17:26Z |
Optimization of broadband RF performance and ESD robustness by pi-model distributed ESD protection scheme
|
Ker, MD; Kuo, BJ; Hsiao, YW |
| 國立交通大學 |
2014-12-08T15:17:09Z |
ESD failure mechanisms of analog I/O cells in 0.18-mu m CMOS technology
|
Ker, MD; Chen, SH; Chuang, CH |
| 國立交通大學 |
2014-12-08T15:16:40Z |
Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes
|
Ker, MD; Chen, SL; Tsai, CS |
| 國立交通大學 |
2014-12-08T15:16:16Z |
Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology
|
Chen, SH; Ker, MD |
| 國立交通大學 |
2014-12-08T15:04:59Z |
A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI
|
WU, CY; KER, MD; LEE, CY; KO, J |
| 國立交通大學 |
2014-12-08T15:04:11Z |
CMOS ON-CHIP ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT USING 4-SCR STRUCTURES WITH LOW ESD-TRIGGER VOLTAGE
|
KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:04:09Z |
TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERION
|
KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:20Z |
MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .1. THEORETICAL DERIVATION
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:20Z |
MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .2. QUANTITATIVE-EVALUATION
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KER, MD; WU, CY |
| 國立交通大學 |
2014-12-08T15:03:16Z |
COMPLEMENTARY-SCR ESD PROTECTION CIRCUIT WITH INTERDIGITATED FINGER-TYPE LAYOUT FOR INPUT PADS OF SUBMICRON CMOS ICS
|
KER, MD; WU, CY |
Showing items 101-125 of 129 (6 Page(s) Totally)
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