| 國立交通大學 |
2014-12-08T15:25:20Z |
Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event
|
Lai, Tai-Xiang; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:18Z |
Low-Leakage Electrostatic Discharge Protection Circuit in 65-nm Fully-Silicided CMOS Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou; Tang, Tien-Hao; Su, Kuan-Cheng |
| 國立交通大學 |
2014-12-08T15:25:06Z |
ESC robustness of 40-V CMOS devices with/without drift implant
|
Chang, Wei-Jen; Ker, Ming-Dou; Lai, Tai-Hsiang; Tang, Tien-Hao; Su, Kuan-Cheng |
| 國立交通大學 |
2014-12-08T15:25:06Z |
Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process
|
Hsu, Sheng-Fu; Ker, Ming-Dou; Lin, Geeng-Lih; Jou, Yeh-Ning |
| 國立交通大學 |
2014-12-08T15:25:06Z |
Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in a 0.25-mu m salicided CMOS process
|
Ker, Ming-Dou; Lai, Tai-Xiang |
| 國立交通大學 |
2014-12-08T15:25:06Z |
Circuit performance degradation of sample-and-hold amplifier due to gate-oxide overstress in a 130-nm CMOS process
|
Chen, Jung-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:03Z |
System-level ESD protection design with on-chip transient detection circuit
|
Yen, Cheng-Cheng; Ker, Ming-Dou; Shih, Pi-Chia |
| 國立交通大學 |
2014-12-08T15:25:03Z |
Study of board-level noise filters to prevent transient-induced latchup in CMOS integrated circuits during EMC/ESD test
|
Hsu, Sheng-Fu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:00Z |
Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-bloc king mask
|
Hsu, Hsin-Chyh; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:00Z |
Method to evaluate Cable Discharge Event (CDE) reliability of integrated circuits in CMOS technology
|
Lai, Tai-Xiang; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:00Z |
ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces
|
Chang, Wei-Jen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:24:59Z |
Gate-oxide reliability on CMOS analog amplifiers in a 130-nm low-voltage CMOS processes
|
Chen, Jung-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:24:57Z |
ESD (Electrostatic Discharge) protection design for nanoelectronics in CMOS technology
|
Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:24:49Z |
The impact of inner pickup on ESD robustness of multi-finger NMOS in nanoscale CMOS technology
|
Ker, Ming-Dou; Hsu, Hsin-Chyh |
| 國立交通大學 |
2014-12-08T15:24:49Z |
Design on new tracking circuit of I/O buffer in 0.13-mu m cell library for mixed-voltage application
|
Chen, Zi-Ping; Chuang, Che-Hao; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:24:44Z |
Low-power wordline voltage generator for low-voltage flash memory
|
Wang, Tzu-Ming; Ker, Ming-Dou; Yeh, Steve; Chang, Ya-Chun |
| 國立交通大學 |
2014-12-08T15:24:43Z |
On-chip transient detection circuit for system-level ESD protection in CMOS ICs
|
Ker, Ming-Dou; Yen, Cheng-Cheng; Shih, Pi-Chia |
| 國立交通大學 |
2014-12-08T15:24:42Z |
Circuit Solutions on ESD Protection Design for Mixed-Voltage I/O Buffers in Nanoscale CMOS
|
Ker, Ming-Dou; Wang, Chang-Tzu |
| 國立交通大學 |
2014-12-08T15:24:40Z |
Design of 2xVDD-Tolerant I/O Buffer with 1xVDD CMOS Devices
|
Ker, Ming-Dou; Lin, Yan-Liang |
| 國立交通大學 |
2014-12-08T15:24:17Z |
Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology
|
Lin, Chun-Yu; Chu, Li-Wei; Tsai, Shiang-Yu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:24:11Z |
Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:23:38Z |
Characterization of SOA in Time Domain and the Improvement Techniques for Using in High-Voltage Integrated Circuits
|
Chen, Wen-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:23:37Z |
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:23:36Z |
Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection
|
Chen, Wen-Yi; Ker, Ming-Dou; Jou, Yeh-Ning; Huang, Yeh-Jen; Lin, Geeng-Lih |
| 國立交通大學 |
2014-12-08T15:23:05Z |
ESD-Aware Circuit Design in CMOS Integrated Circuits to Meet System-Level ESD Specification in Microelectronic Systems
|
Ker, Ming-Dou |
