| 國立交通大學 |
2014-12-08T15:22:57Z |
Transient-to-Digital Converter for Protection Design in CMOS Integrated Circuits against Electrical Fast Transient
|
Yen, Cheng-Cheng; Ker, Ming-Dou; Liao, Chi-Sheng; Chen, Tung-Yang; Tsai, Chih-Chung |
| 國立交通大學 |
2014-12-08T15:22:52Z |
ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process
|
Lin, Chun-Yu; Chu, Li-Wei; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:22:31Z |
On-chip detection circuit for protection design in display panel against electrical fast transient (EFT) disturbance
|
Yen, Cheng-Cheng; Ker, Ming-Dou; Lin, Wan-Yen; Yang, Che-Ming; Chen, Shih-Fan; Chen, Tung-Yang |
| 國立交通大學 |
2014-12-08T15:22:20Z |
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:21:52Z |
Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection
|
Chen, Wen-Yi; Rosenbaum, Elyse; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:21:45Z |
Design and Implementation of Capacitive Sensor Readout Circuit on Glass Substrate for Touch Panel Applications
|
Wang, Tzu-Ming; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:21:45Z |
Layout Styles to Improve CDM ESD Robustness of Integrated Circuits in 65-nm CMOS Process
|
Ker, Ming-Dou; Lin, Chun-Yu; Chang, Tang-Long |
| 國立交通大學 |
2014-12-08T15:20:59Z |
Stimulus driver for epilepsy seizure suppression with adaptive loading impedance
|
Ker, Ming-Dou; Lin, Chun-Yu; Chen, Wei-Ling |
| 國立交通大學 |
2014-12-08T15:20:53Z |
New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels
|
Ker, Ming-Dou; Yen, Cheng-Cheng |
| 國立交通大學 |
2014-12-08T15:20:33Z |
Design of Integrated Gate Driver With Threshold Voltage Drop Cancellation in Amorphous Silicon Technology for TFT-LCD Application
|
Chu, Li-Wei; Liu, Po-Tsun; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:20:29Z |
Impact of Shielding Line on CDM ESD Robustness of Core Circuits in a 65-nm CMOS Process
|
Ker, Ming-Dou; Lin, Chun-Yu; Chang, Tang-Long |
| 國立交通大學 |
2014-12-08T15:16:38Z |
Design on mixed-voltage I/O buffers with consideration of hot-carrier reliability
|
Ker, Ming-Dou; Hu, Fang-Ling |
| 國立交通大學 |
2014-12-08T15:16:31Z |
On-Panel Output Buffer With Offset Compensation Technique for Data Driver in LTPS Technology
|
Ker, Ming-Dou; Deng, Chih-Kang; Huang, Ju-Lin |
| 國立交通大學 |
2014-12-08T15:16:06Z |
New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation
|
Ker, Ming-Dou; Chen, Jung-Sheng |
| 國立交通大學 |
2014-12-08T15:15:50Z |
Component-level measurement for transient-induced latch-up in CMOS ICs under system-level ESD considerations
|
Ker, Ming-Dou; Hsu, Sheng-Fu |
| 國立交通大學 |
2014-12-08T15:15:50Z |
Overview and design of mixed-voltage I/O buffers, with low-voltage thin-oxide CMOS transistors
|
Ker, Ming-Dou; Chen, Shih-Lun; Tsai, Chia-Sheng |
| 國立交通大學 |
2014-12-08T15:15:49Z |
Ultra low-capacitance bond pad for RF applications in CMOS technology
|
Hsiao, Yuan-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:15:40Z |
Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
|
Ker, Ming-Dou; Chen, Wen-Yi; Hsu, Kuo-Chun |
| 國立交通大學 |
2014-12-08T15:15:40Z |
Design of mixed-voltage I/O buffer by using NMOS-blocking technique
|
Ker, Ming-Dou; Chen, Shih-Lun |
| 國立交通大學 |
2014-12-08T15:15:30Z |
Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices
|
Ker, Ming-Dou; Chen, Jia-Huei |
| 國立交通大學 |
2014-12-08T15:15:20Z |
ESD-protection design with extra low-leakage-current diode string for RF circuits in SiGeBiCMOS process
|
Ker, Ming-Dou; Hsiao, Yuan-Wen; Wu, Woei-Lin |
| 國立交通大學 |
2014-12-08T15:15:20Z |
ESD robustness of thin-film devices with different layout structures in LTPS technology
|
Deng, Chih-Kang; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:15:15Z |
Latchup-like failure of power-rail ESD clamp circuits in CMOS integrated circuits under system-level ESD test
|
Ker, Ming-Dou; Yen, Cheng-Cheng |
| 國立交通大學 |
2014-12-08T15:15:12Z |
Failure of on-chip power-fall ESD clamp circuits during system-level ESD test
|
Yen, Cheng-Cheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:15:11Z |
Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes
|
Ker, Ming-Dou; Wang, Chang-Tzu; Tang, Tien-Hao; Su, Kuan-Cbeng |
