| 國立交通大學 |
2014-12-08T15:11:16Z |
Investigation on the validity of holding voltage in high-voltage devices measured by transmission-line-pulsing (TLP)
|
Chen, Wen-Yi; Ker, Ming-Dou; Huang, Yeh-Jen |
| 國立交通大學 |
2014-12-08T15:11:04Z |
Low-capacitance and fast turn-on SCR for RF ESD protection
|
Lin, Chun-Yu; Ker, Ming-Dou; Meng, Guo-Xuan |
| 國立交通大學 |
2014-12-08T15:10:49Z |
Temperature Coefficient of Poly-Silicon TFT and Its Application on Voltage Reference Circuit With Temperature Compensation in LTPS Process
|
Lu, Ting-Chou; Zan, Hsiao-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:10:44Z |
Investigation on Robustness of CMOS Devices Against Cable Discharge Event (CDE) Under Different Layout Parameters in a Deep-Submicrometer CMOS Technology
|
Ker, Ming-Dou; Lai, Tai-Hsiang |
| 國立交通大學 |
2014-12-08T15:10:36Z |
Investigation on Board-Level CDM ESD Issue in IC Products
|
Ker, Ming-Dou; Hsiao, Yuan-Wen |
| 國立交通大學 |
2014-12-08T15:10:12Z |
ESD protection design for giga-Hz high-speed I/O interfaces in a 130-nm CMOS process
|
Hsiao, Yuan-Wen; Ker, Ming-Dou; Chiu, Po-Yen; Huang, Chun; Tseng, Yuh-Kuang |
| 國立交通大學 |
2014-12-08T15:09:54Z |
Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs
|
Lin, Chun-Yu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:50Z |
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:48Z |
Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits
|
Ker, Ming-Dou; Hsiao, Yuan-Wen |
| 國立交通大學 |
2014-12-08T15:09:48Z |
Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes
|
Ker, Ming-Dou; Wang, Chang-Tzu |
| 國立交通大學 |
2014-12-08T15:09:48Z |
Board-Level ESD of Driver ICs on LCD Panel
|
Tseng, Jen-Chou; Hsu, Chung-Ti; Tsai, Chia-Ku; Chen, Shu-Chuan; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:42Z |
High-Voltage nLDMOS in Waffle-Layout Style With Body-Injected Technique for ESD Protection
|
Chen, Wen-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:34Z |
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
|
Chen, Shih-Hung; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:31Z |
A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process
|
Hsiao, Yuan-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:27Z |
Design of mixed-voltage crystal oscillator circuit in low-voltage CMOS technology
|
Ker, Ming-Dou; Liao, Hung-Tai |
| 國立交通大學 |
2014-12-08T15:09:26Z |
Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology
|
Chen, Jung-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:25Z |
Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test
|
Yen, Cheng-Cheng; Ker, Ming-Dou; Chen, Tung-Yang |
| 國立交通大學 |
2014-12-08T15:09:25Z |
The Effect of IEC-Like Fast Transients on RC-Triggered ESD Power Clamps
|
Yen, Cheng-Cheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:22Z |
Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process
|
Hsiao, Yuan-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:20Z |
Test structure on SCR device in waffle layout for RE ESD protection
|
Ker, Ming-Dou; Lin, Chun-Yu |
| 國立交通大學 |
2014-12-08T15:09:16Z |
Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection
|
Chen, Shih-Hung; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:04Z |
Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology
|
Chen, Jung-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:04Z |
Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs
|
Ker, Ming-Dou; Yen, Cheng-Cheng |
| 國立交通大學 |
2014-12-08T15:08:52Z |
Design of Analog Output Buffer With Level Shifting Function on Glass Substrate for Panel Application
|
Wang, Tzu-Ming; Ker, Ming-Dou; Chen, Sao-Chi |
| 國立交通大學 |
2014-12-08T15:08:40Z |
Digital-to-analog converter with gamma correction on glass substrate for TFT-panel applications
|
Wang, Tzu-Ming; Li, Yu-Hsuan; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:08:06Z |
New Ballasting Layout Schemes to Improve ESD Robustness of I/O Buffers in Fully Silicided CMOS Process
|
Ker, Ming-Dou; Chen, Wen-Yi; Shieh, Wuu-Trong; Wei, I-Ju |
| 國立交通大學 |
2014-12-08T15:07:59Z |
Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation
|
Tsai, Hui-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:07:33Z |
New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS
|
Chen, Wen-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:06:56Z |
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
|
Chen, Wen-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:06:51Z |
Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits
|
Yeh, Chih-Ting; Ker, Ming-Dou; Liang, Yung-Chih |
| 國立交通大學 |
2014-12-08T15:06:46Z |
Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-mu m CMOS technology
|
Chen, Shih-Hung; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:06:46Z |
Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme
|
Lin, Chun-Yu; Ker, Ming-Dou; Hsiao, Yuan-Wen |
| 國立交通大學 |
2014-12-08T15:06:44Z |
Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:06:37Z |
High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process
|
Ker, Ming-Dou; Lin, Chun-Yu |
| 國立交通大學 |
2014-12-08T15:05:41Z |
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits
|
Chen, Shih-Hung; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:04:50Z |
New transient detection circuit for system-level ESD protection
|
Yen, Cheng-Cheng; Liao, Chi-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:04:24Z |
Transient Detection Circuit for System-Level ESD Protection and Its On-Board Behavior with EMI/EMC Filters
|
Ker, Ming-Dou; Liao, Chi-Sheng; Yen, Cheng-Cheng |
| 國立交通大學 |
2014-12-08T15:03:56Z |
Transient-to-Digital Converter for ESD Protection Design in Microelectronic Systems
|
Ker, Ming-Dou; Yen, Cheng-Cheng; Liao, Chi-Sheng; Chen, Tung-Yang; Tsai, Chih-Chung |
| 國立交通大學 |
2014-12-08T15:03:22Z |
CDM ESD Protection in CMOS Integrated Circuits
|
Ker, Ming-Dou; Hsiao, Yuan-Wen |
| 國立交通大學 |
2014-12-08T15:02:38Z |
Design of Bandgap Voltage Reference Circuit with all TFT Devices on Glass Substrate in a 3-mu m UPS Process
|
Lu, Ting-Chou; Ker, Ming-Dou; Zan, Hsiao-Wen; Kuo, Chung-Hung; Li, Chun-Huai; Hsieh, Yao-Jen; Liu, Chun-Ting |
| 國立交通大學 |
2014-12-08T15:02:04Z |
Optimization on SCR device with low capacitance for on-chip ESD protection in UWB RF circuits
|
Lin, Chun-Yu; Ker, Ming-Dou |
| 國立成功大學 |
2014-01 |
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control
|
Chen, Wei-Ming; Chiueh, Herming; Chen, Tsan-Jieh; Ho, Chia-Lun; Jeng, Chi; Ker, Ming-Dou; Lin, Chun-Yu; Huang, Ya-Chun; Chou, Chia-Wei; Fan, Tsun-Yuan; Cheng, Ming-Seng; Hsin, Yue-Loong; Liang, Sheng-Fu; Wang, Yu-Lin; Shaw, Fu-Zen; Huang, Yu-Hsing; Yang, Chia-Hsiang; Wu, Chung-Yu |
| 義守大學 |
2009 |
Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process
|
Chiu, Po-Yen ; Ker, Ming-Dou ; Tsai, Fu-Yi ; Chang, Yeong-Jar |
| 義守大學 |
2009 |
Transient-to-digital converter for protection design in CMOS integrated circuits against electrical fast transient
|
Yen, Cheng-Cheng ; Ker, Ming-Dou ; Liao, Chi-Sheng ; Chen, Tung-Yang ; Tsai, Chih-Chung |
| 義守大學 |
2009 |
Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices
|
Ker, Ming-Dou ; Lin, Yan-Liang |
| 義守大學 |
2009 |
On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process
|
Ker, Ming-Dou ; Chiu, Po-Yen ; Tsai, Fu-Yi ; Chang, Yeong-Jar |
| 義守大學 |
2009 |
Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology
|
Wang, Chang-Tzu ; Ker, Ming-Dou ; Tang, Tien-Hao ; Su, Kuan-Cheng |
| 義守大學 |
2009 |
Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection
|
Chen, Wen-Yi ; Ker, Ming-Dou ; Jou, Yeh-Ning ; Huang, Yeh-Jen ; Lin, Geeng-Lih |
| 義守大學 |
2001-06 |
Design of on-chip power-rail ESD clamp circuit with ultra-small capacitance to detect ESD transition
|
Chen, Shih-Hung ; Ker, Ming-Dou |
| 義守大學 |
1999-07 |
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS
|
Ker, Ming-Dou ; Wang, Chang-Tzu |
