| 國立交通大學 |
2014-12-08T15:09:26Z |
Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology
|
Chen, Jung-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:25Z |
Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test
|
Yen, Cheng-Cheng; Ker, Ming-Dou; Chen, Tung-Yang |
| 國立交通大學 |
2014-12-08T15:09:25Z |
The Effect of IEC-Like Fast Transients on RC-Triggered ESD Power Clamps
|
Yen, Cheng-Cheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:22Z |
Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process
|
Hsiao, Yuan-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:20Z |
Test structure on SCR device in waffle layout for RE ESD protection
|
Ker, Ming-Dou; Lin, Chun-Yu |
| 國立交通大學 |
2014-12-08T15:09:16Z |
Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection
|
Chen, Shih-Hung; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:04Z |
Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology
|
Chen, Jung-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:09:04Z |
Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs
|
Ker, Ming-Dou; Yen, Cheng-Cheng |
| 國立交通大學 |
2014-12-08T15:08:52Z |
Design of Analog Output Buffer With Level Shifting Function on Glass Substrate for Panel Application
|
Wang, Tzu-Ming; Ker, Ming-Dou; Chen, Sao-Chi |
| 國立交通大學 |
2014-12-08T15:08:40Z |
Digital-to-analog converter with gamma correction on glass substrate for TFT-panel applications
|
Wang, Tzu-Ming; Li, Yu-Hsuan; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:08:06Z |
New Ballasting Layout Schemes to Improve ESD Robustness of I/O Buffers in Fully Silicided CMOS Process
|
Ker, Ming-Dou; Chen, Wen-Yi; Shieh, Wuu-Trong; Wei, I-Ju |
| 國立交通大學 |
2014-12-08T15:07:59Z |
Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation
|
Tsai, Hui-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:07:33Z |
New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS
|
Chen, Wen-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:06:56Z |
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
|
Chen, Wen-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:06:51Z |
Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits
|
Yeh, Chih-Ting; Ker, Ming-Dou; Liang, Yung-Chih |
| 國立交通大學 |
2014-12-08T15:06:46Z |
Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-mu m CMOS technology
|
Chen, Shih-Hung; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:06:46Z |
Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme
|
Lin, Chun-Yu; Ker, Ming-Dou; Hsiao, Yuan-Wen |
| 國立交通大學 |
2014-12-08T15:06:44Z |
Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:06:37Z |
High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process
|
Ker, Ming-Dou; Lin, Chun-Yu |
| 國立交通大學 |
2014-12-08T15:05:41Z |
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits
|
Chen, Shih-Hung; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:04:50Z |
New transient detection circuit for system-level ESD protection
|
Yen, Cheng-Cheng; Liao, Chi-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:04:24Z |
Transient Detection Circuit for System-Level ESD Protection and Its On-Board Behavior with EMI/EMC Filters
|
Ker, Ming-Dou; Liao, Chi-Sheng; Yen, Cheng-Cheng |
| 國立交通大學 |
2014-12-08T15:03:56Z |
Transient-to-Digital Converter for ESD Protection Design in Microelectronic Systems
|
Ker, Ming-Dou; Yen, Cheng-Cheng; Liao, Chi-Sheng; Chen, Tung-Yang; Tsai, Chih-Chung |
| 國立交通大學 |
2014-12-08T15:03:22Z |
CDM ESD Protection in CMOS Integrated Circuits
|
Ker, Ming-Dou; Hsiao, Yuan-Wen |
| 國立交通大學 |
2014-12-08T15:02:38Z |
Design of Bandgap Voltage Reference Circuit with all TFT Devices on Glass Substrate in a 3-mu m UPS Process
|
Lu, Ting-Chou; Ker, Ming-Dou; Zan, Hsiao-Wen; Kuo, Chung-Hung; Li, Chun-Huai; Hsieh, Yao-Jen; Liu, Chun-Ting |
