| 國立交通大學 |
2014-12-08T15:15:50Z |
Overview and design of mixed-voltage I/O buffers, with low-voltage thin-oxide CMOS transistors
|
Ker, Ming-Dou; Chen, Shih-Lun; Tsai, Chia-Sheng |
| 國立交通大學 |
2014-12-08T15:15:49Z |
Ultra low-capacitance bond pad for RF applications in CMOS technology
|
Hsiao, Yuan-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:15:40Z |
Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
|
Ker, Ming-Dou; Chen, Wen-Yi; Hsu, Kuo-Chun |
| 國立交通大學 |
2014-12-08T15:15:40Z |
Design of mixed-voltage I/O buffer by using NMOS-blocking technique
|
Ker, Ming-Dou; Chen, Shih-Lun |
| 國立交通大學 |
2014-12-08T15:15:30Z |
Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices
|
Ker, Ming-Dou; Chen, Jia-Huei |
| 國立交通大學 |
2014-12-08T15:15:20Z |
ESD-protection design with extra low-leakage-current diode string for RF circuits in SiGeBiCMOS process
|
Ker, Ming-Dou; Hsiao, Yuan-Wen; Wu, Woei-Lin |
| 國立交通大學 |
2014-12-08T15:15:20Z |
ESD robustness of thin-film devices with different layout structures in LTPS technology
|
Deng, Chih-Kang; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:15:15Z |
Latchup-like failure of power-rail ESD clamp circuits in CMOS integrated circuits under system-level ESD test
|
Ker, Ming-Dou; Yen, Cheng-Cheng |
| 國立交通大學 |
2014-12-08T15:15:12Z |
Failure of on-chip power-fall ESD clamp circuits during system-level ESD test
|
Yen, Cheng-Cheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:15:11Z |
Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes
|
Ker, Ming-Dou; Wang, Chang-Tzu; Tang, Tien-Hao; Su, Kuan-Cbeng |
| 國立交通大學 |
2014-12-08T15:15:10Z |
Bond pad design with low capacitance in CMOS technology for RF applications
|
Hsiao, Yuan-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:14:59Z |
An output buffer for 3.3-V applications in a 0.13-mu m 1/2.5-V CMOS process
|
Chen, Shih-Lun; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:14:59Z |
Ultra-high-voltage charge pump circuit in low-voltage bulk CMOS processes with polysilicon diodes
|
Ker, Ming-Dou; Chen, Shih-Lun |
| 國立交通大學 |
2014-12-08T15:14:59Z |
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology
|
Ker, Ming-Dou; Chang, Wei-Jen |
| 國立交通大學 |
2014-12-08T15:14:26Z |
Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs
|
Hsu, Sheng-Fu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:14:09Z |
Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology
|
Ker, Ming-Dou; Chen, Shih-Hung |
| 國立交通大學 |
2014-12-08T15:13:50Z |
Fabrication of a miniature CMOS-based optical biosensor
|
Ho, Wei-Jen; Chen, Jung-Sheng; Ker, Ming-Dou; Wu, Tung-Kung; Wu, Chung-Yu; Yang, Yuh-Shyong; Li, Yaw-Kuen; Yuan, Chiun-Jye |
| 國立交通大學 |
2014-12-08T15:13:37Z |
Transient-induced latchup dependence on power-pin damping frequency and damping factor in CMOS integrated circuits
|
Hsu, Sheng-Fu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:13:26Z |
New gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process
|
Chen, Jung-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:13:23Z |
On-chip ESD protection design for automotive vacuum-fluorescent-display (VFD) driver IC to sustain high ESD stress
|
Ker, Ming-Dou; Chang, Wei-Jen |
| 國立交通大學 |
2014-12-08T15:13:16Z |
A new architecture for charge pump circuit without suffering gate-oxide reliability in low-voltage CMOS processes
|
Wang, Tzu-Ming; Shen, Wan-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:13:13Z |
Design of 2xVDD-tolerant I/O buffer with considerations of gate-oxide reliability and hot-carrier degradation
|
Tsai, Hui-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:13:09Z |
The impact of gate-oxide breakdown on common-source-amplifiers with diode-connected active load in low-voltage CMOS processes
|
Chen, Jung-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:12:38Z |
Transient-induced latchup in CMOS integrated circuits due to electrical fast transient (EFT) test
|
Yen, Cheng-Cheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:12:37Z |
On-chip transient detection circuit for system-level ESD protection in CMOS integrated circuits to meet electromagnetic compatibility regulation
|
Ker, Ming-Dou; Yen, Cheng-Cheng; Shih, Pi-Chia |
