| 國立交通大學 |
2014-12-08T15:42:34Z |
Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses
|
Chen, Shih-Hung; Ker, Ming-Dou; Hung, Hsiang-Pin |
| 國立交通大學 |
2014-12-08T15:42:19Z |
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
|
Ker, Ming-Dou; Yen, Cheng-Cheng |
| 國立交通大學 |
2014-12-08T15:41:28Z |
Design and Realization of Delta-Sigma Analog-to-Digital Converter in LTPS Technology
|
Tsai, Chia-Chi; Ker, Ming-Dou; Li, Yu-Hsuan; Kuo, Chung-Hung; Li, Chun-Huai; Hsieh, Yao-Jen; Liu, Chun-Ting |
| 國立交通大學 |
2014-12-08T15:41:15Z |
DESIGN OF ON-CHIP POWER-RAIL ESD CLAMP CIRCUIT WITH ULTR-SMALL CAPACITANCE TO DETECT ESD TRANSITION
|
Chen, Shih-Hung; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:40:31Z |
Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology
|
Wang, Tzu-Ming; Ker, Ming-Dou; Liao, Hung-Tai |
| 國立交通大學 |
2014-12-08T15:39:26Z |
A BENDING N-WELL BALLAST LAYOUT TO IMPROVE ESD ROBUSTNESS IN FULLY-SILICIDED CMOS TECHNOLOGY
|
Wen, Yong-Ru; Ker, Ming-Dou; Chen, Wen-Yi |
| 國立交通大學 |
2014-12-08T15:39:08Z |
Self-Matched ESD Cell in CMOS Technology for 60-GHz Broadband RF Applications
|
Lin, Chun-Yu; Chu, Li-Wei; Ker, Ming-Dou; Lu, Tse-Hua; Hung, Ping-Fang; Li, Hsiao-Chun |
| 國立交通大學 |
2014-12-08T15:38:52Z |
ESD Protection Circuit for High-Voltage CMOS ICs with Improved Immunity Against Transient-Induced Latchup
|
Ker, Ming-Dou; Hsu, Che-Lun; Chen, Wen-Yi |
| 國立交通大學 |
2014-12-08T15:38:45Z |
2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Low Standby Leakage in 65-nm CMOS Process
|
Lin, Chun-Yu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:38:25Z |
ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:37:35Z |
Design of Analog Pixel Memory for Low Power Application in TFT-LCDs
|
Chu, Li-Wei; Liu, Po-Tsun; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:37:32Z |
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs
|
Ker, Ming-Dou; Chen, Wen-Yi; Shieh, Wuu-Trong; Wei, I-Ju |
| 國立交通大學 |
2014-12-08T15:36:53Z |
Study on ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Applications
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:36:23Z |
Evaluation of subcortical grey matter abnormalities in patients with MRI-negative cortical epilepsy determined through structural and tensor magnetic resonance imaging
|
Peng, Syu-Jyun; Harnod, Tomor; Tsai, Jang-Zern; Ker, Ming-Dou; Chiou, Jun-Chern; Chiueh, Herming; Wu, Chung-Yu; Hsin, Yue-Loong |
| 國立交通大學 |
2014-12-08T15:36:21Z |
Local CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applications
|
Chen, Shih-Hung; Linten, Dimitri; Scholz, Mirko; Huang, Yu-Ching; Hellings, Geert; Boschke, Roman; Ker, Ming-Dou; Groeseneken, Guido |
| 國立交通大學 |
2014-12-08T15:36:20Z |
Investigating electron depletion effect in amorphous indium-gallium-zinc-oxide thin-film transistor with a floating capping metal by technology computer-aided design simulation and leakage reduction
|
Lu, Ting-Chou; Chen, Wei-Tsung; Zan, Hsiao-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:36:10Z |
Through Diffusion Tensor Magnetic Resonance Imaging to Evaluate the Original Properties of Neural Pathways of Patients with Partial Seizures and Secondary Generalization by Individual Anatomic Reference Atlas
|
Peng, Syu-Jyun; Harnod, Tomor; Tsai, Jang-Zern; Huang, Chien-Chun; Ker, Ming-Dou; Chiou, Jun-Chern; Chiueh, Herming; Wu, Chung-Yu; Hsin, Yue-Loong |
| 國立交通大學 |
2014-12-08T15:36:01Z |
On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection
|
Chuang, Che-Hao; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:35:55Z |
Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits
|
Tsai, Hui-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:35:55Z |
On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
|
Ker, Ming-Dou; Yeh, Chih-Ting |
| 國立交通大學 |
2014-12-08T15:35:49Z |
Design of high-voltage-tolerant stimulus driver with adaptive loading consideration to suppress epileptic seizure in a 0.18-mu m CMOS process
|
Lin, Chun-Yu; Li, Yi-Ju; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:35:37Z |
Synthesis of uniform core-shell gelatin-alginate microparticles as intestine-released oral delivery drug carrier
|
Huang, Keng-Shiang; Yang, Chih-Hui; Kung, Chao-Ping; Grumezescu, Alexandru Mihai; Ker, Ming-Dou; Lin, Yung-Sheng; Wang, Chih-Yu |
| 國立交通大學 |
2014-12-08T15:35:09Z |
Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit
|
Chiu, Po-Yen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:35:09Z |
SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance
|
Ker, Ming-Dou; Lin, Wan-Yen; Yen, Cheng-Cheng |
| 國立交通大學 |
2014-12-08T15:33:56Z |
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control
|
Chen, Wei-Ming; Chiueh, Herming; Chen, Tsan-Jieh; Ho, Chia-Lun; Jeng, Chi; Ker, Ming-Dou; Lin, Chun-Yu; Huang, Ya-Chun; Chou, Chia-Wei; Fan, Tsun-Yuan; Cheng, Ming-Seng; Hsin, Yue-Loong; Liang, Sheng-Fu; Wang, Yu-Lin; Shaw, Fu-Zen; Huang, Yu-Hsing; Yang, Chia-Hsiang; Wu, Chung-Yu |
