| 國立交通大學 |
2014-12-08T15:33:13Z |
Analysis and Solution to Overcome EOS Failure Induced by Latchup Test in A High-Voltage Integrated Circuits
|
Tsai, Hui-Wen; Ker, Ming-Dou; Liu, Yi-Sheng; Chuang, Ming-Nan |
| 國立交通大學 |
2014-12-08T15:33:12Z |
Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm CMOS Technology
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:33:10Z |
Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies
|
Ker, Ming-Dou; Lin, Chun-Yu; Hsiao, Yuan-Wen |
| 國立交通大學 |
2014-12-08T15:32:53Z |
Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process
|
Lin, Chun-Yu; Chu, Li-Wei; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:32:18Z |
Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process
|
Altolaguirre, Federico Agustin; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:32:16Z |
Design of 2 x V-DD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 x V-DD Thin-Oxide Devices
|
Ker, Ming-Dou; Chiu, Po-Yen |
| 國立交通大學 |
2014-12-08T15:32:12Z |
Investigation on Safe Operating Area and ESD Robustness in a 60-V BCD Process with Different Deep P-Well Test Structures
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:30:51Z |
Design and implementation of readout circuit on glass substrate with digital correction for touch-panel applications
|
Wang, Tzu-Ming; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:30:45Z |
Self-Protected LDMOS Output Device with Embedded SCR to Improve ESD Robustness in 0.25-mu m 60-V BCD Process
|
Huang, Yu-Ching; Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:30:43Z |
Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability
|
Lin, Chun-Yu; Chen, Wei-Ling; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:30:41Z |
A Latchup-Immune and Robust SCR Device for ESD Protection in 0.25-mu m 5-V CMOS Process
|
Huang, Yu-Ching; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:30:24Z |
High Area-Efficient ESD Clamp Circuit With Equivalent RC-Based Detection Mechanism in a 65-nm CMOS Process
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:30:06Z |
Compact and Low-Loss ESD Protection Design for V-Band RF Applications in a 65-nm CMOS Technology
|
Chu, Li-Wei; Lin, Chun-Yu; Tsai, Shiang-Yu; Ker, Ming-Dou; Song, Ming-Hsiang; Jou, Chewn-Pu; Lu, Tse-Hua; Tseng, Jen-Chou; Tsai, Ming-Hsien; Hsu, Tsun-Lai; Hung, Ping-Fang; Chang, Tzu-Heng |
| 國立交通大學 |
2014-12-08T15:30:04Z |
Design of Negative High Voltage Generator for Biphasic Stimulator with SoC Integration Consideration
|
Huang, Ya-Chun; Ker, Ming-Dou; Lin, Chun-Yu |
| 國立交通大學 |
2014-12-08T15:30:04Z |
Live Demonstration: Implantable Stimulator for Epileptic Seizure Suppression with Loading Impedance Adaptability
|
Ker, Ming-Dou; Chen, Wei-Ling; Lin, Chun-Yu |
| 國立交通大學 |
2014-12-08T15:30:03Z |
Design of ESD Protection for RF CMOS Power Amplifier with Inductor in Matching Network
|
Tsai, Shiang-Yu; Lin, Chun-Yu; Chu, Li-Wei; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:29:54Z |
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:29:51Z |
Design of Dual-Band ESD Protection for 24-/60-GHz Millimeter-Wave Circuits
|
Chu, Li-Wei; Lin, Chun-Yu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:29:32Z |
Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
|
Lin, Chun-Yu; Tsai, Shiang-Yu; Chu, Li-Wei; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:29:23Z |
Digital time-modulation pixel memory circuit in LTPS technology
|
Chen, Szu-Han; Ker, Ming-Dou; Wang, Tzu-Ming |
| 國立交通大學 |
2014-12-08T15:28:53Z |
Foreword for the Special Issue on ESD Technology
|
Boselli, Gianluca; Ker, Ming-Dou; Duvvury, Charvaka |
| 國立交通大學 |
2014-12-08T15:28:43Z |
Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process
|
Lin, Chun-Yu; Chu, Li-Wei; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:28:41Z |
Failure Analysis on Gate-Driven ESD Clamp Circuit after TLP Stresses of Different Voltage Steps in a 16-V CMOS Process
|
Dai, Chia-Tsen; Chiu, Po-Yen; Ker, Ming-Dou; Tsai, Fu-Yi; Peng, Yan-Hua; Tsai, Chia-Ku |
| 國立交通大學 |
2014-12-08T15:28:40Z |
Design of ESD Protection Cell for Dual-Band RF Applications in a 65-nm CMOS Process
|
Chu, Li-Wei; Lin, Chun-Yu; Tsai, Shiang-Yu; Ker, Ming-Dou; Song, Ming-Hsiang; Jou, Chewn-Pu; Lu, Tse-Hua; Tseng, Jen-Chou; Tsai, Ming-Hsien; Hsu, Tsun-Lai; Hung, Ping-Fang; Chang, Tzu-Heng; Wei, Yu-Lin |
| 國立交通大學 |
2014-12-08T15:28:34Z |
Investigation on CDM ESD events at core circuits in a 65-nm CMOS process
|
Lin, Chun-Yu; Chang, Tang-Long; Ker, Ming-Dou |
