| 國立交通大學 |
2014-12-08T15:28:28Z |
Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:28:05Z |
ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process
|
Lin, Chun-Yu; Chu, Li-Wei; Ker, Ming-Dou; Song, Ming-Hsiang; Jou, Chewn-Pu; Lu, Tse-Hua; Tseng, Jen-Chou; Tsai, Ming-Hsien; Hsu, Tsun-Lai; Hung, Ping-Fang; Chang, Tzu-Heng |
| 國立交通大學 |
2014-12-08T15:28:04Z |
New Design of Transient-Noise Detection Circuit with SCR Device for System-Level ESD Protection
|
Ker, Ming-Dou; Lin, Wan-Yen |
| 國立交通大學 |
2014-12-08T15:28:04Z |
High-Voltage-Tolerant Stimulator with Adaptive Loading Consideration for Electronic Epilepsy Prosthetic SoC in a 0.18-mu m CMOS Process
|
Lin, Chun-Yu; Li, Yi-Ju; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:27:35Z |
Improving Safe Operating Area of nLDMOS Array With Embedded Silicon Controlled Rectifier for ESD Protection in a 24-V BCD Process
|
Chen, Wen-Yi; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:27:19Z |
New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process
|
Ker, Ming-Dou; Chiu, Po-Yen |
| 國立交通大學 |
2014-12-08T15:25:35Z |
Initial-on ESD protection design with PMOS-triggered SCR device
|
Ker, Ming-Dou; Chen, Shih-Hung |
| 國立交通大學 |
2014-12-08T15:25:20Z |
On-chip high-voltage charge pump circuit in standard CMOS processes with polysilicon diodes
|
Ker, Ming-Dou; Chen, Shih-Lun |
| 國立交通大學 |
2014-12-08T15:25:20Z |
ESD protection design for mixed-voltage I/O interfaces - Overview
|
Ker, Ming-Dou; Lin, Kun-Hsien |
| 國立交通大學 |
2014-12-08T15:25:20Z |
Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process
|
Chiu, Po-Yen; Ker, Ming-Dou; Tsai, Fu-Yi; Chang, Yeong-Jar |
| 國立交通大學 |
2014-12-08T15:25:20Z |
Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event
|
Lai, Tai-Xiang; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:18Z |
Low-Leakage Electrostatic Discharge Protection Circuit in 65-nm Fully-Silicided CMOS Technology
|
Wang, Chang-Tzu; Ker, Ming-Dou; Tang, Tien-Hao; Su, Kuan-Cheng |
| 國立交通大學 |
2014-12-08T15:25:06Z |
ESC robustness of 40-V CMOS devices with/without drift implant
|
Chang, Wei-Jen; Ker, Ming-Dou; Lai, Tai-Hsiang; Tang, Tien-Hao; Su, Kuan-Cheng |
| 國立交通大學 |
2014-12-08T15:25:06Z |
Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process
|
Hsu, Sheng-Fu; Ker, Ming-Dou; Lin, Geeng-Lih; Jou, Yeh-Ning |
| 國立交通大學 |
2014-12-08T15:25:06Z |
Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in a 0.25-mu m salicided CMOS process
|
Ker, Ming-Dou; Lai, Tai-Xiang |
| 國立交通大學 |
2014-12-08T15:25:06Z |
Circuit performance degradation of sample-and-hold amplifier due to gate-oxide overstress in a 130-nm CMOS process
|
Chen, Jung-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:03Z |
System-level ESD protection design with on-chip transient detection circuit
|
Yen, Cheng-Cheng; Ker, Ming-Dou; Shih, Pi-Chia |
| 國立交通大學 |
2014-12-08T15:25:03Z |
Study of board-level noise filters to prevent transient-induced latchup in CMOS integrated circuits during EMC/ESD test
|
Hsu, Sheng-Fu; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:00Z |
Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-bloc king mask
|
Hsu, Hsin-Chyh; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:00Z |
Method to evaluate Cable Discharge Event (CDE) reliability of integrated circuits in CMOS technology
|
Lai, Tai-Xiang; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:00Z |
ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces
|
Chang, Wei-Jen; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:24:59Z |
Gate-oxide reliability on CMOS analog amplifiers in a 130-nm low-voltage CMOS processes
|
Chen, Jung-Sheng; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:24:57Z |
ESD (Electrostatic Discharge) protection design for nanoelectronics in CMOS technology
|
Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:24:49Z |
The impact of inner pickup on ESD robustness of multi-finger NMOS in nanoscale CMOS technology
|
Ker, Ming-Dou; Hsu, Hsin-Chyh |
| 國立交通大學 |
2014-12-08T15:24:49Z |
Design on new tracking circuit of I/O buffer in 0.13-mu m cell library for mixed-voltage application
|
Chen, Zi-Ping; Chuang, Che-Hao; Ker, Ming-Dou |
