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Showing items 391-400 of 400 (16 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:02:04Z |
Optimization on SCR device with low capacitance for on-chip ESD protection in UWB RF circuits
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Lin, Chun-Yu; Ker, Ming-Dou |
| 國立成功大學 |
2014-01 |
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control
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Chen, Wei-Ming; Chiueh, Herming; Chen, Tsan-Jieh; Ho, Chia-Lun; Jeng, Chi; Ker, Ming-Dou; Lin, Chun-Yu; Huang, Ya-Chun; Chou, Chia-Wei; Fan, Tsun-Yuan; Cheng, Ming-Seng; Hsin, Yue-Loong; Liang, Sheng-Fu; Wang, Yu-Lin; Shaw, Fu-Zen; Huang, Yu-Hsing; Yang, Chia-Hsiang; Wu, Chung-Yu |
| 義守大學 |
2009 |
Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process
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Chiu, Po-Yen ; Ker, Ming-Dou ; Tsai, Fu-Yi ; Chang, Yeong-Jar |
| 義守大學 |
2009 |
Transient-to-digital converter for protection design in CMOS integrated circuits against electrical fast transient
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Yen, Cheng-Cheng ; Ker, Ming-Dou ; Liao, Chi-Sheng ; Chen, Tung-Yang ; Tsai, Chih-Chung |
| 義守大學 |
2009 |
Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices
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Ker, Ming-Dou ; Lin, Yan-Liang |
| 義守大學 |
2009 |
On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process
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Ker, Ming-Dou ; Chiu, Po-Yen ; Tsai, Fu-Yi ; Chang, Yeong-Jar |
| 義守大學 |
2009 |
Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology
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Wang, Chang-Tzu ; Ker, Ming-Dou ; Tang, Tien-Hao ; Su, Kuan-Cheng |
| 義守大學 |
2009 |
Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection
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Chen, Wen-Yi ; Ker, Ming-Dou ; Jou, Yeh-Ning ; Huang, Yeh-Jen ; Lin, Geeng-Lih |
| 義守大學 |
2001-06 |
Design of on-chip power-rail ESD clamp circuit with ultra-small capacitance to detect ESD transition
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Chen, Shih-Hung ; Ker, Ming-Dou |
| 義守大學 |
1999-07 |
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS
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Ker, Ming-Dou ; Wang, Chang-Tzu |
Showing items 391-400 of 400 (16 Page(s) Totally)
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