| 國立交通大學 |
2018-01-24T07:38:40Z |
應用於抑制癲癇發作之雙模式刺激器系統設計
|
顏鼎洋; 柯明道; Yen, Ting-Yang; Ker, Ming-Dou |
| 國立交通大學 |
2018-01-24T07:38:35Z |
低電壓觸發矽控整流器在靜電放電防護上的設計與應用
|
吳易翰; 柯明道; Wu, Yi-Han; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:56:42Z |
A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process
|
Luo, Zhicong; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:56:36Z |
ESD Protection Design for Touch Panel Control IC Against Latchup-Like Failure Induced by System-Level ESD Test
|
Ker, Ming-Dou; Chiu, Po-Yen; Shieh, Wuu-Trong; Wang, Chun-Chi |
| 國立交通大學 |
2017-04-21T06:56:35Z |
Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:56:27Z |
Low-Leakage Bidirectional SCR With Symmetrical Trigger Circuit for ESD Protection in 40-nm CMOS Process
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:56:16Z |
A 8 Phases 192 MHz Crystal-Less Clock Generator with PVT Calibration
|
Lu, Ting-Chou; Ker, Ming-Dou; Zan, Hsiao-Wen; Liu, Jen-Chieh; Lee, Yu |
| 國立交通大學 |
2017-04-21T06:56:09Z |
A 8 Phases 192 MHz Crystal-Less Clock Generator with PVT Calibration
|
Lu, Ting-Chou; Ker, Ming-Dou; Zan, Hsiao-Wen; Liu, Jen-Chieh; Lee, Yu |
| 國立交通大學 |
2017-04-21T06:55:58Z |
Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High-k Metal Gate CMOS Process
|
Lin, Chun-Yu; Wu, Yi-Han; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:55:39Z |
Quad-SCR Device for Cross-Domain ESD Protection
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:55:39Z |
Investigation of Human-Body-Model and Machine-Model ESD Robustness on Stacked Low-Voltage Field-Oxide Devices for High-Voltage Applications
|
Huang, Yi-Jie; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:55:35Z |
ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:50:10Z |
ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Pins of Battery-Monitoring IC
|
Dai, Chia-Tsen; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:50:01Z |
Design of AC-Coupled Circuit for High-speed Interconnects
|
Huang, Chun-Wei; Liu, Kai-Jen; Huang, Yu-Jung; Chen, Ming-Kun; Lin, Yi-Lung; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:50:01Z |
Design of Power-Rail ESD Clamp Circuit with Adjustable Holding Voltage against Mis-trigger or Transient-Induced Latch-On Events
|
Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:50:00Z |
SCR Device for On-Chip ESD Protection in RF Power Amplifier
|
Lin, Chun-Yu; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:50:00Z |
On-Chip ESD Protection Designs in RF Integrated Circuits for Radio and Wireless Applications
|
Ker, Ming-Dou; Lin, Chun-Yu |
| 國立交通大學 |
2017-04-21T06:49:53Z |
Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits
|
Yeh, Chih-Ting; Liang, Yung-Chih; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:51Z |
Improve Latch-up Immunity by Circuit Solution
|
Tsai, Hui-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:47Z |
Area-Efficient Power-Rail ESD Clamp Circuit with SCR Device Embedded into ESD-Transient Detection Circuit in a 65nm CMOS Process
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:46Z |
Study on the ESD-Induced Gate-Oxide Breakdown and the Protection Solution in 28nm High-K Metal-Gate CMOS Technology
|
Lin, Chun-Yu; Ker, Ming-Dou; Chang, Pin-Hsin; Wang, Wen-Tai |
| 國立交通大學 |
2017-04-21T06:49:46Z |
Resistor-Less Power-Rail ESD Clamp Circuit with Ultra-Low Leakage Current in 65nm CMOS Process
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:43Z |
Automation of synchronous bias transmission line pulsing system
|
Chang, Bor-Wei; Hsu, Hsin-Chyh; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:33Z |
On the Design of Power-Rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-Voltage CMOS Process
|
Ker, Ming-Dou; Chiu, Po-Yen; Tsai, Fu-Yi; Chang, Yeong-Jar |
| 國立交通大學 |
2017-04-21T06:49:29Z |
Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free Immunity
|
Tang, Kai-Neng; Liao, Seian-Feng; Ker, Ming-Dou; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih |
