| 國立交通大學 |
2017-04-21T06:49:46Z |
Study on the ESD-Induced Gate-Oxide Breakdown and the Protection Solution in 28nm High-K Metal-Gate CMOS Technology
|
Lin, Chun-Yu; Ker, Ming-Dou; Chang, Pin-Hsin; Wang, Wen-Tai |
| 國立交通大學 |
2017-04-21T06:49:46Z |
Resistor-Less Power-Rail ESD Clamp Circuit with Ultra-Low Leakage Current in 65nm CMOS Process
|
Yeh, Chih-Ting; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:43Z |
Automation of synchronous bias transmission line pulsing system
|
Chang, Bor-Wei; Hsu, Hsin-Chyh; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:33Z |
On the Design of Power-Rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-Voltage CMOS Process
|
Ker, Ming-Dou; Chiu, Po-Yen; Tsai, Fu-Yi; Chang, Yeong-Jar |
| 國立交通大學 |
2017-04-21T06:49:29Z |
Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free Immunity
|
Tang, Kai-Neng; Liao, Seian-Feng; Ker, Ming-Dou; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih |
| 國立交通大學 |
2017-04-21T06:49:20Z |
Vertical SCR Structure for On-Chip ESD Protection in Nanoscale CMOS Technology
|
Lin, Chun-Yu; Chang, Pin-Hsin; Chang, Rong-Kun; Ker, Ming-Dou; Wang, Wen-Tai |
| 國立交通大學 |
2017-04-21T06:49:12Z |
CMOS power amplifier with ESD protection design merged in matching network
|
Shiu, Yu-Da; Huang, Bo-Shih; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:12Z |
ESD Protection Design with Latchup-Free Immunity in 120V SOI Process
|
Huang, Yi-Jie; Ker, Ming-Dou; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih |
| 國立交通大學 |
2017-04-21T06:49:05Z |
Compensation Circuit with Additional Junction Sensor to Enhance Latchup Immunity for CMOS Integrated Circuits
|
Tsai, Hui-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:49:05Z |
Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection
|
Liao, Seian-Feng; Tang, Kai-Neng; Ker, Ming-Dou; Yeh, Jia-Rong; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih |
| 國立交通大學 |
2017-04-21T06:49:02Z |
A 70nW, 0.3V Temperature Compensation Voltage Reference Consisting of Subthreshold MOSFETs in 65nm CMOS Technology
|
Lu, Ting-Chou; Ker, Ming-Dou; Zan, Hsiao-Wen |
| 國立交通大學 |
2017-04-21T06:48:45Z |
ESD Protection Design for Wideband RF Applications in 65-nm CMOS Process
|
Chu, Li-Wei; Lin, Chun-Yu; Ker, Ming-Dou; Song, Ming-Hsiang; Tseng, Jen-Chou; Jou, Chewn-Pu; Tsai, Ming-Hsien |
| 國立交通大學 |
2017-04-21T06:48:42Z |
Improving ESD Robustness of Stacked Diodes with Embedded SCR for RF Applications in 65-nm CMOS
|
Lin, Chun-Yu; Fan, Mei-Lian; Ker, Ming-Dou; Chu, Li-Wei; Tseng, Jen-Chou; Song, Ming-Hsiang |
| 國立交通大學 |
2017-04-21T06:48:27Z |
Active ESD Protection for Input Transistors in a 40-nm CMOS Process
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:48:25Z |
Investigation on RF characteristics of stacked P-I-N polysilicon diodes for ESD protection design in 0.18-mu m CMOS technology
|
Shiu, Yu-Da; Chuang, Che-Hao; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:48:21Z |
Design of High-Voltage-Tolerant Level Shifter in Low Voltage CMOS Process for Neuro Stimulator
|
Luo, Zhicong; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:48:20Z |
ESD Self-Protection Design on 2.4-GHz T/R Switch for RF Application in CMOS Process
|
Lin, Chun-Yu; Liu, Rui-Hong; Ker, Ming-Dou |
| 國立交通大學 |
2017-04-21T06:48:17Z |
On-Chip ESD Protection Design for HV Integrated Circuits
|
Ker, Ming-Dou |
| 國立交通大學 |
2016-03-28T08:17:51Z |
前瞻性混合信號式電路設計技術開發---總計畫暨子計畫五：前瞻性靜電放電防護技術開發
|
柯明道; KER MING-DOU |
| 國立交通大學 |
2016-03-28T00:05:45Z |
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic SoC for Real-Time Epileptic Seizure Control
|
Chen, Wei-Ming; Chiueh, Herming; Chen, Tsan-Jieh; Ho, Chia-Lun; Jeng, Chi; Chang, Shun-Ting; Ker, Ming-Dou; Lin, Chun-Yu; Huang, Ya-Chun; Chou, Chia-Wei; Fan, Tsun-Yuan; Cheng, Ming-Seng; Liang, Sheng-Fu; Chien, Tzu-Chieh; Wu, Sih-Yen; Wang, Yu-Lin; Shaw, Fu-Zen; Huang, Yu-Hsing; Yang, Chia-Hsiang; Chiou, Jin-Chern; Chang, Chih-Wei; Chou, Lei-Chun; Wu, Chung-Yu |
| 國立交通大學 |
2016-03-28T00:04:24Z |
Area-Efficient and Low-Leakage Diode String for On-Chip ESD Protection
|
Lin, Chun-Yu; Wu, Po-Han; Ker, Ming-Dou |
| 國立交通大學 |
2015-12-04T07:03:17Z |
ACTIVE GUARD RING STRUCTURE TO IMPROVE LATCH-UP IMMUNITY
|
KER MING-DOU; TSAI HUI-WEN |
| 國立交通大學 |
2015-12-02T02:59:12Z |
Area-Efficient ESD Clamp Circuit With a Capacitance-Boosting Technique to Minimize Standby Leakage Current
|
Altolaguirre, Federico A.; Ker, Ming-Dou |
| 國立交通大學 |
2015-12-02T02:59:12Z |
Latch-Up Protection Design With Corresponding Complementary Current to Suppress the Effect of External Current Triggers
|
Tsai, Hui-Wen; Ker, Ming-Dou |
| 國立交通大學 |
2015-11-26T01:06:58Z |
應用於低溫多晶矽製程下電容式感測器讀出電路設計與實現
|
林佑達; Lin, Yu-Ta; 柯明道; Ker, Ming-Dou |
