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亞洲大學 |
201310 |
Design of a low on resistance high voltage (<100V) novel 3D NLDMOS with side STI and single P-top layer based on 0.18um BCD Process Technology
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Kumar, Ankit;Kumar, Ankit;Yulia, Emita;Hapsari, Emita Yulia;Kuma, Vasanth;Kumar, Vasanth;Mri, Aryadeep;Mrinal, Aryadeep;許健;Sheu, Gene;楊紹明;Yang, Shao-Ming;Ningar, Vivek;Ningaraju, Vivek |
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