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Institution	Date	Title	Author
臺大學術典藏	2004-07	Evolution of low-voltage CMOS digital VLSI circuits using bootstrap technique	Kuo, J.B.Kuojb; Kuo, J.B.; KuoJB
臺大學術典藏	2003-11	Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect	Kuo, J.B.; Sun, E.C.; Lin, M.T.Kuojb; Kuo, J.B.; Sun, E.C.; Lin, M.T.; KuoJB
臺大學術典藏	2000-06	SPICE compact modeling of PD-SOI CMOS devices	Kuo, J.B.; Kuo, J.B.; KuoJB
臺大學術典藏	1997-10	Compact current model for mesa-isolated fully-depleted ultrathin SOI NMOS devices considering sidewall-related narrow channel effects	Kuo, J.B.; Su, K.W.; Kuo, J.B.; Su, K.W.; KuoJB
臺大學術典藏	1995-09	A high-speed 1.5 V clocked BiCMOS latch for BiCMOS dynamic pipelined digital logic VLSI systems	Kuo, J.B.; Lou, J.H.; Su, K.W.; Kuo, J.B.; Lou, J.H.; Su, K.W.; KuoJB
臺大學術典藏	1994-07	A radical-partitioned neural network system using a modified Sigmoid function and a weight-dotted radical selector for large-volume Chinese characters recognition VLSI	Kuo, J.B.; Chen, B.Y.; Mao, M.W.; Kuo, J.B.; Chen, B.Y.; Mao, M.W.; KuoJB
臺大學術典藏	1994-06	A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5 V full-swing BiCMOS dynamic logic circuit	Kuo, J.B.; Su, K.W.; Lou, J.H.; Kuo, J.B.; Su, K.W.; Lou, J.H.; KuoJB
臺大學術典藏	1994-05	Device-level analysis of a BiPMOS pull-down device structure for low-voltage dynamic BiCMOS VLSI	Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; Kuo, J.B.; Su, K.W.; Lou, J.H.; Ma, Y.; Chen, S.S.; Chiang, C.S.; KuoJB
臺大學術典藏	1994-02	Closed-form physical model for VLSI bipolar devices considering energy transport	Kuo, J.B.; Huang, H.J.; Lu, T.C.; Kuo, J.B.; Huang, H.J.; Lu, T.C.; KuoJB
臺大學術典藏	1994-01	Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers	Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; Kuo, J.B.; Wang, J.Y.; Chen, Y.G.; KuoJB
臺大學術典藏	1993-11	1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture	KuoJB; Su, K.W.; Lou, J.H.; Kuo, J.B.; Kuo, J.B.; Su, K.W.; Lou, J.H.
臺大學術典藏	1993-11	Amorphous silicon TFT capacitance model using an effective temperature approach	Kuo, J.B.; Chen, S.S.; Kuo, J.B.; Chen, S.S.; KuoJB
臺大學術典藏	1993-10	Saturation region model for a-Si:H TFTs using a quasi-two-dimensional approach	Kuo, J.B.; Chen, S.S.; Kuo, J.B.; Chen, S.S.; KuoJB
臺大學術典藏	1993-10	An analytical back gate bias dependent threshold voltage model for SiGe-channel ultra-thin SOI PMOS devices	Kuo, J.B.; Tang, M.C.; Sim, J.H.; Kuo, J.B.; Tang, M.C.; Sim, J.H.; KuoJB
臺大學術典藏	1993-08	Analytical drain current model for a-Si:H TFTs by simultaneously considering localised deep and tail states	Kuo, J.B.; Chen, C.S.; Kuo, J.B.; Chen, C.S.; KuoJB
臺大學術典藏	1993-05	A BiCMOS dynamic divider circuit using a nonrestoring iterative architecture with carry look ahead for CPU VLSI	Kuo, J.B.; Chen, H.P.; Huang, H.J.; Kuo, J.B.; Chen, H.P.; Huang, H.J.; KuoJB
臺大學術典藏	1993-05	Accumulation-type vs. inversion-type of an ultra-thin SIO PMOS device operating at 300 K and 77 K: subthreshold behavior and pull-up switching performance of a CMOS inverter	Kuo, J.B.; Sim, J.H.; Kuo, J.B.; Sim, J.H.; KuoJB
臺大學術典藏	1992-10	A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture	Kuo, J.B.; Liao, H.J.; Chen, H.P.; Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB
臺大學術典藏	1992-10	Delayed-turn-on phenomenon in accumulation-type SOI pMOS device operating at liquid nitrogen temperature	Kuo, J.B.; Sim, J.H.; Kuo, J.B.; Sim, J.H.; KuoJB
臺大學術典藏	1992-06	A radical-partitioned coded block adaptive neural network structure for large-volume Chinese characters recognition	Kuo, J.B.; Mao, M.W.; Kuo, J.B.; Mao, M.W.; KuoJB
臺大學術典藏	1992-02	BiCMOS dynamic Manchester carry look ahead circuit for high speed arithmetic unit VLSI	Kuo, J.B.; Liao, H.J.; Chen, H.P.; KuoJB; Kuo, J.B.; Liao, H.J.; Chen, H.P.
臺大學術典藏	1991-09	A BiCMOS tristate buffer for high-speed microprocessor VLSI	Kuo, J.B.; Liao, H.J.; Kuo, J.B.; Liao, H.J.; KuoJB
臺大學術典藏	1991-09	Device-level transient analysis of a 1 μm six-transistor BiCMOS inverter circuit using a large-scale quasi-3D device simulator	Kuo, J.B.; Chen, Y.W.Kuojb; Kuo, J.B.; Chen, Y.W.; KuoJB
臺大學術典藏	1991-07	BiCMOS edge detector with correlated-double-sampling readout circuit for pattern recognition neural network	Kuo, J.B.; Chou, T.L.; Wong, E.J.; Kuo, J.B.; Chou, T.L.; Wong, E.J.; KuoJB
臺大學術典藏	1991-06	A structured adaptive neural network for pattern recognition VLSI	Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C.; Kuo, J.B.; Wong, E.J.; Chen, C.C.; Hsiao, C.C.; KuoJB
臺大學術典藏	1991-05	Device-level analysis of a 1 μm BiCMOS inverter circuit operating at 77 K using a modified PISCES program	Kuo, J.B.; Chen, Y.W.; Lou, K.H.; Kuo, J.B.; Chen, Y.W.; Lou, K.H.; KuoJB
臺大學術典藏	1991-05	A coded block adaptive neural network structure for pattern recognition VLSI	Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C.; KuoJB; Kuo, J.B.; Chen, Y.K.; Lu, Y.H.; Mao, W.C

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