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Showing items 1-7 of 7 (1 Page(s) Totally)
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| 臺大學術典藏 |
2020-06-11T06:50:39Z |
On pre/post-bond testing and calibrating SAR ADC array in 3-D CMOS imager
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Huang, X.-L.;Kang, P.-Y.;Huang, J.-L.;Chou, Y.-F.;Lee, Y.-P.;Kwai, D.-M.; Huang, X.-L.; Kang, P.-Y.; Huang, J.-L.; Chou, Y.-F.; Lee, Y.-P.; Kwai, D.-M.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-01-13T08:23:07Z |
Design and implementation of 3D-thermal test chip for exploration of package effects
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Chien, J.-H.; Lung, C.-L.; Lin, T.-W.; Tsai, K.-J.; Chen, T.-S.; Chou, Y.-F.; Chen, P.-H.; Chang, S.-C.; Kwai, D.-M.; PING-HEI CHEN |
| 臺大學術典藏 |
2020-01-13T08:23:07Z |
Realization of virtual 126-core system with thermal sensor-network using metallic thermal skeletons
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Chien, J.-H.; Lung, C.-L.; Tsai, K.-J.; Hsu, C.-C.; Chen, T.-S.; Chou, Y.-F.; Chen, P.-H.; Chang, S.-C.; Kwai, D.-M.; PING-HEI CHEN |
| 臺大學術典藏 |
2020-01-13T08:23:06Z |
Thermal stress aware design for stacking IC with through glass via
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Chien, J.-H.; Yu, H.; Lung, C.-L.; Chang, H.-C.; Tsai, N.-Y.; Chou, Y.-F.; Chen, P.-H.; Chang, S.-C.; Kwai, D.-M.; PING-HEI CHEN |
| 臺大學術典藏 |
2020-01-13T08:23:06Z |
Hybrid thermal solution for 3D-ICs: Using thermal TSVs with placement algorithm for stress relieving structures
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Chien, J.-H.; Yu, H.; Tsai, N.-Y.; Lung, C.-L.; Hsu, C.-C.; Chou, Y.-F.; Chen, P.-H.; Chang, S.-C.; Kwai, D.-M.; PING-HEI CHEN |
| 臺大學術典藏 |
2018-09-10T09:18:50Z |
Hybrid thermal solution for 3D-ICs: Using thermal TSVs with placement algorithm for stress relieving structures
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Chien, J.-H.; Yu, H.; Tsai, N.-Y.; Lung, C.-L.; Hsu, C.-C.; Chou, Y.-F.; Chen, P.-H.; Chang, S.-C.; Kwai, D.-M.; PING-HEI CHEN |
| 臺大學術典藏 |
2018-09-10T08:37:34Z |
Realization of virtual 126-core system with thermal sensor-network using metallic thermal skeletons
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Chien, J.-H.; Lung, C.-L.; Tsai, K.-J.; Hsu, C.-C.; Chen, T.-S.; Chou, Y.-F.; Chen, P.-H.; Chang, S.-C.; Kwai, D.-M.; PING-HEI CHEN |
Showing items 1-7 of 7 (1 Page(s) Totally)
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