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Taiwan Academic Institutional Repository >
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"lai chieh ming"
Showing items 11-17 of 17 (2 Page(s) Totally)
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| 國立成功大學 |
2007-02 |
A novel strain method for enhancement of 90-nm node and beyond FUSI-gated CMOS performance
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Lin, Chien-Ting; Fang, Yean-Kuen; Yeh, Wen-Kuan; Lee, Tung-Hsing; Chen, Ming-Shing; Lai, Chieh-Ming; Hsu, Che-Hua; Chen, Liang-Wei; Cheng, Li-Wei; Ma, Mike |
| 國立成功大學 |
2006-11 |
The geometry effect of contact etch stop layer impact on device performance and reliability for 90-nm SOI nMOSFETs
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Lai, Chieh-Ming; Fang, Yean-Kuen; Lin, Chien-Ting; Yeh, Wen-Kuan |
| 國立成功大學 |
2006-06 |
The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90 nm SOI nMOSFETs
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Lai, Chieh-Ming; Fang, Yean-Kuen; Lin, Chien-Ting; Hsu, Chia-Wei; Yeh, Wen-Kuan |
| 國立成功大學 |
2006-04 |
Stress technology impact on device performances and reliability for (100) sub-90 nm silicon-on-insulator complementary metal-oxide-semiconductor field-effect-transistors
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Lai, Chieh-Ming; Fang, Yean-Kuen; Yeh, Wen-Kuan |
| 國立高雄大學 |
2006 |
The impact of stress enhanced technology for sub-90nm SOI MOSFETs
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Yeh, Wen-Kuan; Lai, Chieh-Ming; Lin, Chien-Ting; Fang, Yean-Kuen |
| 國立成功大學 |
2005-04 |
Width effect on hot-carrier-induced degradation for 90nm partially depleted SOICMOSFETs
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Lai, Chieh-Ming; Fang, Yean-Kuen; Pan, Shing-Tai; Yeh, Wen-Kuan |
| 國立高雄大學 |
2005 |
Stress technology impact on device performance and reliability for <100> sub-90nm SOI CMOSFETs
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Yeh, Wen-Kuan; Lai, Chieh-Ming; Lin, Chien-Ting; Fang, Yean-Kuen; Shiau, W.T. |
Showing items 11-17 of 17 (2 Page(s) Totally)
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