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Showing items 1-4 of 4 (1 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:25:20Z |
Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event
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Lai, Tai-Xiang; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:25:06Z |
Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in a 0.25-mu m salicided CMOS process
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Ker, Ming-Dou; Lai, Tai-Xiang |
| 國立交通大學 |
2014-12-08T15:25:00Z |
Method to evaluate Cable Discharge Event (CDE) reliability of integrated circuits in CMOS technology
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Lai, Tai-Xiang; Ker, Ming-Dou |
| 國立交通大學 |
2014-12-08T15:12:36Z |
The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process
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Chang, Wei-Jen; Ker, Ming-Dou; Lai, Tai-Xiang; Tang, Tien-Hao; Su, Kuan-Cheng |
Showing items 1-4 of 4 (1 Page(s) Totally)
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