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"lee chen yi"的相关文件
显示项目 301-310 / 328 (共33页)
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| 國立交通大學 |
2014-12-08T15:13:09Z |
An ultra-low-power and portable digitally controlled oscillator for SoC applications
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Sheng, Duo; Chung, Ching-Che; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:12:45Z |
Design of an H.264/AVC decoder with memory hierarchy and line-pixel-lookahead
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Liu, Tsu-Ming; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:12:37Z |
An indexed-scaling pipelined FFT processor for OFDM-based WPAN applications
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Chen, Yuan; Tsao, Yu-Chi; Lin, Yu-Wei; Lin, Chin-Hung; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:12:31Z |
An LDPC decoder chip based on self-routing network for IEEE 802.16e applications
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Liu, Chih-Hao; Yen, Shau-Wei; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi; Hsu, Yar-Sun; Jou, Shyh-Jye |
| 國立交通大學 |
2014-12-08T15:10:57Z |
A symbol-rate timing synchronization method for low power wireless OFDM systems
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Yu, Jui-Yuan; Chung, Ching-Che; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:10:14Z |
An all-digital phase-frequency tunable clock generator for wireless OFDM communications systems
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Yu, Jui-Yuan; Chen, Juinn-Ting; Yang, Mei-Hui; Chung, Ching-Che; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:10:02Z |
A joint architecture of error-concealed deblocking filter for H.264/AVC video transmission
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Lee, Wen-Ping; Liu, Tsu-Ming; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:08:46Z |
A Universal VLSI Architecture for ReedSolomon Error-and-Erasure Decoders
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Chang, Hsie-Chia; Lin, Chien-Ching; Chang, Fu-Ke; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:08:46Z |
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network
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Liu, Chih-Hao; Lin, Chien-Ching; Yen, Shau-Wei; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi; Hsu, Yar-Sun; Jou, Shyh-Jye |
| 國立交通大學 |
2014-12-08T15:08:26Z |
A 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaver
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Wong, Cheng-Chi; Tang, Cheng-Hao; Lai, Ming-Wei; Zheng, Yan-Xiu; Lin, Chien-Ching; Chang, Hsie-Chia; Lee, Chen-Yi; Su, Yu-T. |
显示项目 301-310 / 328 (共33页)
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