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Taiwan Academic Institutional Repository >
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"lee jri"
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| 臺大學術典藏 |
2020-06-11T07:06:12Z |
Tutorial: "Design of high-speed wireline transceivers".
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Lee, Jri; Lee, Jri; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:10Z |
A 2 x 25-Gb/s Receiver With 2:5 DMUX for 100-Gb/s Ethernet
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Wu, Ke-Chung;Lee, Jri; Wu, Ke-Chung; Lee, Jri; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:10Z |
W-Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology
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Huang, Shih-Jou;Yeh, Yu-Ching;Wang, Huaide;Chen, Pang-Ning;Lee, Jri; Huang, Shih-Jou; Yeh, Yu-Ching; Wang, Huaide; Chen, Pang-Ning; Lee, Jri; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
Study of Subharmonically Injection-Locked PLLs
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Lee, Jri;Wang, Huaide; Lee, Jri; Wang, Huaide; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:09Z |
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition
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Lee, Jri;Wu, Ke-Chung; Lee, Jri; Wu, Ke-Chung; JRI LEE |
| 臺大學術典藏 |
2020-06-11T07:06:05Z |
A 20Gb/s Duobinary Transceiver in 90nm CMOS.
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Lee, Jri;Chen, Ming-Shuan;Wang, Huaide; Lee, Jri; Chen, Ming-Shuan; Wang, Huaide; JRI LEE |
| 臺大學術典藏 |
2010 |
A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology
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Lee, Jri;Li, Yi-An;Hung, Meng-Hsiung;Huang, Shih-Jou; Lee, Jri; Li, Yi-An; Hung, Meng-Hsiung; Huang, Shih-Jou; JRI LEE |
| 國立臺灣大學 |
2008-09 |
Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary
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Lee, Jri; Chen, M.; Wang, H. |
| 國立臺灣大學 |
2008-06 |
A 75-GHz Phase-Locked Loop in 90-nm CMOS Technique
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Lee, Jri; Liu, M.; Wang, H. |
| 國立臺灣大學 |
2008-03 |
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
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Lee, Jri; Liu, M. |
Showing items 1-10 of 23 (3 Page(s) Totally)
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