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Showing items 1-8 of 8 (1 Page(s) Totally)
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| 國立交通大學 |
2017-04-21T06:49:50Z |
A 1.31Gb/s, 96.6% Utilization Stochastic Nonbinary LDPC Decoder for Small Cell Applications
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Lee, Xin-Ru; Yang, Chih-Wen; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi |
| 國立交通大學 |
2015-11-26T00:55:33Z |
隨機二位元與非二位元低密度同位元檢查碼解碼器之研究
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李欣儒; Lee, Xin-Ru; 李鎮宜; 張錫嘉; Lee, Chen-Yi; Chang, Hsie-Chia |
| 國立交通大學 |
2015-07-21T08:31:30Z |
Area-efficient TFM-based Stochastic Decoder Design for Non-binary LDPC Codes
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Yang, Chih-Wen; Lee, Xin-Ru; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi |
| 國立交通大學 |
2015-07-21T08:29:01Z |
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications
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Lee, Xin-Ru; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi |
| 國立交通大學 |
2015-07-21T08:28:43Z |
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes
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Lee, Xin-Ru; Yang, Chih-Wen; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-12T01:27:19Z |
以脈波閂鎖器之存活記憶體單元為基礎之低功率維特比解碼器
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李欣儒; Lee, Xin-Ru; 李鎮宜; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:30:06Z |
Stochastic Decoding for LDPC Convolutional Codes
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Lee, Xin-Ru; Chen, Chih-Lung; Chang, Hsie-Chia; Lee, Chen-Yi |
| 國立交通大學 |
2014-12-08T15:20:31Z |
A Low-Power Radix-4 Viterbi Decoder Based on DCVSPG Pulsed Latch with Sharing Technique
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Lee, Xin-Ru; Chang, Hsie-Chia; Lee, Chen-Yi |
Showing items 1-8 of 8 (1 Page(s) Totally)
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