| 臺大學術典藏 |
2018-09-10T04:59:51Z |
A Design for Testability Technique for Low Power Delay Fault Testing
|
Li, J. C. M.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:13Z |
A multicircuit simulator based on inverse jacobian matrix reuse
|
Lee, H.-I.;Han, C.-Y.;Li, J.C.-M.; Lee, H.-I.; Han, C.-Y.; Li, J.C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T08:34:44Z |
An accurate timing-aware diagnosis algorithm for multiple small delay defects
|
Chen, P.-J.;Hsu, W.-L.;Li, J.C.-M.;Tseng, N.-H.;Chen, K.-Y.;Changchien, W.-P.;Liu, C.C.C.; Chen, P.-J.; Hsu, W.-L.; Li, J.C.-M.; Tseng, N.-H.; Chen, K.-Y.; Changchien, W.-P.; Liu, C.C.C.; WEI-LI HSU; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-30T02:49:18Z |
An accurate timing-aware diagnosis algorithm for multiple small delay defects
|
Chen P.-J. ;Wei-Li Hsu ;Li J.C.-M. ;Tseng N.-H. ;Chen K.-Y. ;Changchien W.-P. ;Liu C.C.C.; Chen P.-J.; WEI-LI HSU; Li J.C.-M.; Tseng N.-H.; Chen K.-Y.; Changchien W.-P.; Liu C.C.C. |
| 臺大學術典藏 |
2020-06-11T06:45:49Z |
An at-speed self-testable technique for the high speed domino adder
|
Wang, Y.-S.;Hsieh, M.-H.;Liu, C.-M.;Liu, C.-W.;Li, J.C.-M.;Chen, C.C.-P.; Wang, Y.-S.; Hsieh, M.-H.; Liu, C.-M.; Liu, C.-W.; Li, J.C.-M.; Chen, C.C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-29T01:20:15Z |
ATPG and test compression for probabilistic circuits
|
Wu, C.-H.; Li, J.C.-M.; CHIEN-MO LI; Yang, K.-C.;Lee, M.-T.;Wu, C.-H.;Li, J.C.-M.; Yang, K.-C.; Lee, M.-T. |
| 臺大學術典藏 |
2020-06-29T01:20:17Z |
Automatic test pattern generation
|
Cheng, K.-T.T.;Wang, L.-C.;Li, H.;Li, J.C.-M.; Cheng, K.-T.T.; Wang, L.-C.; Li, H.; Li, J.C.-M.; CHIEN-MO LI |
| 國立臺灣大學 |
2005-11 |
Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chains
|
Lin, Hung-Mao; Li, J.C.M. |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
CSER: BISER-based concurrent soft-error resilience
|
Laung-Terng Wang;Touba, N.A.;Zhigang Jiang;Shianling Wu;Jiun-Lang Huang;Li, J.C.-M.; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI; JIUN-LANG HUANG |
| 國立臺灣大學 |
2010 |
DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-in
|
Kao, Wei-Chung; Chuang, Wei-Shun; Lin, Hsiu-Ting; Li, J.C.-M.; Manquinho, V. |
| 臺大學術典藏 |
2018-09-10T04:15:41Z |
Diagnosis for Sequence Dependent Chips
|
Li, J. C.M.; E. J. McCluskey; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T05:29:21Z |
Diagnosis of Multiple Hold-time and Setup-time Faults in Scan Chains
|
Li, J. C. M.; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T05:29:21Z |
Diagnosis of Resistive and Stuck-open Defects in Digital CMOS IC
|
Li, J. C.-M.; E. J. McCluskey; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T05:29:21Z |
Diagnosis of Single stuck-at Faults and Multiple Timing Faults in Scan Chains
|
Li, J. C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2018-09-10T03:50:57Z |
Diagnosis of Tunneling Opens
|
Li, J. C.M.; E.J. McCluskey; CHIEN-MO LI |
| 臺大學術典藏 |
2021-09-02T00:04:09Z |
Diagnosis technique for Clustered Multiple Transition Delay Faults
|
You Y.-S;Liu C.-Y;Wu M.-T;Chen P.-W;Li J.C.-M.; You Y.-S; Liu C.-Y; Wu M.-T; Chen P.-W; Li J.C.-M.; CHIEN-MO LI |
| 國立臺灣大學 |
2008 |
Effective and Economic Phase Noise Testing for Single-Chip TV Tuners
|
Li, J. C.-M.; Lin, P.-C.; Chiang, P.-C.; Pan, C.-M.; Tseng, C.W. |
| 臺大學術典藏 |
2019-04-22T05:22:34Z |
Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction
|
Jiang, J.-H.R.;Li, J.C.M.;Pai, Y.-C.;Wen, H.-T.;Wang, J.-J.;Pai, C.-C.;Wang, R.-Y.;Chang, Y.-W.; Wang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W.; Li, J.C.M.; Jiang, J.-H.R. |
| 臺大學術典藏 |
2020-06-29T01:20:09Z |
Fault Simulation and Test Generation
|
Li, J.C.-M.;Hsiao, M.S.; Li, J.C.-M.; Hsiao, M.S.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:10Z |
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits
|
Chiang, K.-Y.;Ho, Y.-H.;Chen, Y.-W.;Pan, C.-S.;Li, J.C.-M.; Chiang, K.-Y.; Ho, Y.-H.; Chen, Y.-W.; Pan, C.-S.; Li, J.C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2021-09-02T00:04:09Z |
High Efficiency and Low Overkill Testing for Probabilistic Circuits
|
Lee M.-T;Wu C.-H;Liu S.-T;Hsieh C.-Y;Li J.C.-M.; Lee M.-T; Wu C.-H; Liu S.-T; Hsieh C.-Y; Li J.C.-M.; CHIEN-MO LI |
| 國立臺灣大學 |
2005-05 |
Jump scan: a DFT technique for low power testing
|
Chiu, Min-Hao; Li, J.C.M. |
| 臺大學術典藏 |
2020-06-29T01:20:15Z |
Parallel order ATPG for test compaction
|
Chen, Y.-W.;Ho, Y.-H.;Chang, C.-M.;Yang, K.-C.;Li, M.-T.;Li, J.C.-M.; Chen, Y.-W.; Ho, Y.-H.; Chang, C.-M.; Yang, K.-C.; Li, M.-T.; Li, J.C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-29T01:20:12Z |
Placement optimization of flexible TFT digital circuits
|
Liu, W.-H.;Ma, E.-H.;Wei, W.-E.;Li, J.C.-M.; Liu, W.-H.; Ma, E.-H.; Wei, W.-E.; Li, J.C.-M.; CHIEN-MO LI |
| 臺大學術典藏 |
2021-09-02T00:04:09Z |
QATG: Automatic Test Generation for Quantum Circuits
|
Wu C.-H;Hsieh C.-Y;Li J.-Y;Li J.C.-M.; Wu C.-H; Hsieh C.-Y; Li J.-Y; Li J.C.-M.; CHIEN-MO LI |
