| 臺大學術典藏 |
2018-09-10T05:15:50Z |
Advances in hardware architectures for image and video coding - A survey
|
Tseng, P.-C.; Chang, Y.-C.; Huang, Y.-W.; Fang, H.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:50Z |
VLSI-based array dividers with concurrent error detection
|
Chen, T.-H.; Lee, Y.-P.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:49Z |
Architecture of global motion compensation for MPEG-4 advanced simple profile
|
Chen, Y.-H.; Chen, C.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:49Z |
Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos
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Chen, T.-W.; Huang, Y.-W.; Chen, T.-C.; Chen, Y.-H.; Tsai, C.-Y.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:49Z |
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder
|
Huang, Y.-W.; Hsieh, B.-Y.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:49Z |
Analysis and architecture for memory efficient JBIG2 arithmetic encoder
|
Chen, C.-C.; Chang, Y.-W.; Fang, H.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Hardware architecture design of video compression for multimedia communication systems
|
Chen, Liang-Gee; Chen, Homer H.; Chen, Ching-Yeh; Huang, Yu-Wen; LIANG-GEE CHEN; Chien, Shao-Yi; Chien, Shao-Yi; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Four field variable block size motion compensated adaptive de-interlacing
|
Chang, Yu-Lin; Chen, Ching-Yeh; Lin, Shyh-Feng; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Fast filterbanks for the low power MPEG high efficiency advanced audio coding decoder
|
Huang, S.-W.; Tsai, T.-H.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:48Z |
Fast decomposition of filterbanks for the state-of-the-art audio coding
|
Huang, S.-W.; Tsai, T.-H.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:47Z |
Memory efficient JPEG 2000 architecture with stripe pipeline scheme
|
Fang, H.-C.; Chang, Y.-W.; Cheng, C.-C.; Chen, C.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:47Z |
Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering
|
Huang, C.-T.; Chen, C.-Y.; Chen, Y.-H.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:47Z |
JPEG, MPEG-4, and H.264 codec IP development
|
Lian, Chung-Jr; Huang, Yu-Wen; Fang, Hung-Chi; Chang, Yung-Chi; Chen, Liang-Gee; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:47Z |
Hybrid-mode embedded compression for H.264/AVC video coding system
|
Chen, T.-C.; Chen, Y.-H.; Wu, K.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:47Z |
Hardware oriented content-adaptive fast algorithm for variable block-size integer motion estimation in H.264
|
Chen, Y.-H.; Chen, T.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
Parallel embedded block coding architecture for JPEG 2000
|
Fang, H.-C.; Chang, Y.-W.; Wang, T.-C.; Lian, C.-J.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
One-pass computation-aware motion estimation with adaptive search strategy
|
Huang, Y.W.; Lee, C.L.; Chen, C.Y.; Chen, L.G.; LIANG-GEE CHEN; Lee, Chia-Lin |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
Nearly lossless content-dependent low-power DCT design for mobile video applications
|
Lin, C.-P.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
Multiple-lifting Scheme: Memory-efficient VLSI implementation for line-based 2-D DWT
|
Cheng, C.-C.; Huang, C.-T.; Tseng, P.-C.; Pan, C.-H.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:46Z |
Multi-mode embedded compression codec engine for power-aware video coding system
|
Cheng, C.-C.; Tseng, P.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:45Z |
Special issue on advances in video coding and delivery
|
Zhu, W.; Sun, M.-T.; Chen, L.-G.; Sikora, T.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:45Z |
Reconfigurable discrete wavelet transform processor for heterogeneous reconfigurable multimedia systems
|
Tseng, P.-C.;Huang, C.-T.;Chen, L.-G.; Tseng, P.-C.; Huang, C.-T.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:44Z |
VLSI architecture for forward discrete wavelet transform based on B-spline factorization
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:44Z |
VLSI architecture for fifting-based shape-adaptive discrete wavelet transform with odd-symmetric filters
|
Huang, C.-T.; Tseng, P.-C.; Chen, L.-G.; LIANG-GEE CHEN |
