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Institution Date Title Author
臺大學術典藏 2003-11 Analysis of gate misalignment effect on the threshold voltage of double-gate (DG) ultrathin fully-depleted (FD) silicon-on-insulator (SOI) NMOS devices using a compact model considering fringing electric field effect Kuo, J.B.; Sun, E.C.; Lin, M.T.Kuojb; Kuo, J.B.; Sun, E.C.; Lin, M.T.; KuoJB

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