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"liu s i"的相关文件
显示项目 16-25 / 144 (共15页)
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| 臺大學術典藏 |
2020-06-11T06:34:57Z |
Ultrasonic wireless power and data communication for neural stimulation
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Tsai, J.-Y.;Huang, K.-H.;Wang, J.-R.;Liu, S.-I.;Li, P.-C.; Tsai, J.-Y.; Huang, K.-H.; Wang, J.-R.; Liu, S.-I.; Li, P.-C.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:56Z |
A 12-bit 3.4 MS/s two-step cyclic time-domain ADC in 0.18-μm CMOS
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Chen, L.-J.;Liu, S.-I.; Chen, L.-J.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:56Z |
An On-Chip Relaxation Oscillator with Comparator Delay Compensation
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Chang, Y.-A.;Adiono, T.;Hamidah, A.;Liu, S.-I.; Chang, Y.-A.; Adiono, T.; Hamidah, A.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:56Z |
A PVT-Tolerant Injection-Locked Clock Multiplier with a Frequency Calibrator Using a Delay Time Detector
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Tien, C.-W.;Liu, S.-I.; Tien, C.-W.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:56Z |
A 2.4-GHz frequency-drift-compensated phase-locked loop with 2.43 ppm/°C temperature coefficient
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Hsieh, C.-E.;Liu, S.-I.; Hsieh, C.-E.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:55Z |
A Subharmonically Injection-Locked All-Digital PLL Without Main Divider
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Zeng, K.-H.;Kuan, T.-K.;Liu, S.-I.; Zeng, K.-H.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:55Z |
A 10-bit 40-MS/s Time-Domain Two-Step ADC with Short Calibration Time
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Chen, L.-J.;Liu, S.-I.; Chen, L.-J.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 20-MHz to 3-GHz wide-range multiphase delay-locked loop
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Chuang, C.-N.;Liu, S.-I.; Chuang, C.-N.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 20-Gb/s transmitter with adaptive preemphasis in 65-nm CMOS technology
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Kao, S.-Y.;Liu, S.-I.; Kao, S.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 132.6-GHz phase-locked loop in 65 nm digital CMOS
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Lin, B.-Y.;Liu, S.-I.; Lin, B.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
显示项目 16-25 / 144 (共15页)
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