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"liu s i"的相关文件
显示项目 26-35 / 144 (共15页)
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| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 3-25 Gb/s four-channel receiver with noise-canceling TIA and power-scalable sLA
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Chien, Y.-H.;Fu, K.-L.;Liu, S.-I.; Chien, Y.-H.; Fu, K.-L.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:53Z |
A leakage-compensated PLL in 65-nm CMOS technology
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Hung, C.-C.;Liu, S.-I.; Hung, C.-C.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:52Z |
A 10-20 Gb/s CDR circuit with 6200ppm frequency tracking
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Huang, C.-C.;Tseng, K.-W.;Liu, S.-I.; Huang, C.-C.; Tseng, K.-W.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:52Z |
A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer with a Fast-Converging Correlation Loop
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Tseng, Y.-H.;Yeh, C.-W.;Liu, S.-I.; Tseng, Y.-H.; Yeh, C.-W.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:52Z |
A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis
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Su, W.-J.;Liu, S.-I.; Su, W.-J.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:51Z |
A Bang-Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques
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Kuan, T.-K.;Liu, S.-I.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:51Z |
A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS
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Hsieh, M.-H.; Chen, L.-H.; Liu, S.-I.; Chen, C.C.-P.; SHEN-IUAN LIU; Hsieh, M.-H.;Chen, L.-H.;Liu, S.-I.;Chen, C.C.-P. |
| 臺大學術典藏 |
2020-06-11T06:34:51Z |
A Voltage Multiplier With Adaptive Threshold Voltage Compensation
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Luo, Y.-S.;Liu, S.-I.; Luo, Y.-S.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:50Z |
A 33.6-to-33.8 Gb/s burst-mode CDR in 90 nm CMOS technology
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Cho, L.-C.;Lee, C.;Hung, C.-C.;Liu, S.-I.; Cho, L.-C.; Lee, C.; Hung, C.-C.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:50Z |
A 1.5 GHz all-digital spread-spectrum clock generator
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Lin, S.-Y.;Liu, S.-I.; Lin, S.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
显示项目 26-35 / 144 (共15页)
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