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"liu s i"的相關文件
顯示項目 31-40 / 144 (共15頁)
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| 臺大學術典藏 |
2020-06-11T06:34:51Z |
A Bang-Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques
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Kuan, T.-K.;Liu, S.-I.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:51Z |
A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS
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Hsieh, M.-H.; Chen, L.-H.; Liu, S.-I.; Chen, C.C.-P.; SHEN-IUAN LIU; Hsieh, M.-H.;Chen, L.-H.;Liu, S.-I.;Chen, C.C.-P. |
| 臺大學術典藏 |
2020-06-11T06:34:51Z |
A Voltage Multiplier With Adaptive Threshold Voltage Compensation
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Luo, Y.-S.;Liu, S.-I.; Luo, Y.-S.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:50Z |
A 33.6-to-33.8 Gb/s burst-mode CDR in 90 nm CMOS technology
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Cho, L.-C.;Lee, C.;Hung, C.-C.;Liu, S.-I.; Cho, L.-C.; Lee, C.; Hung, C.-C.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:50Z |
A 1.5 GHz all-digital spread-spectrum clock generator
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Lin, S.-Y.;Liu, S.-I.; Lin, S.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:49Z |
A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control
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Luo, Y.-S.;Lin, H.-H.;Liu, S.-I.; Luo, Y.-S.; Lin, H.-H.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:49Z |
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing
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Lee, I.-T.;Chen, Y.-J.;Liu, S.-I.;Jou, C.-P.;Hsueh, F.-L.;Hsieh, H.-H.; Lee, I.-T.; Chen, Y.-J.; Liu, S.-I.; Jou, C.-P.; Hsueh, F.-L.; Hsieh, H.-H.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:49Z |
A silicon nanowire-based bio-sensing system with digitized outputs for acute myocardial infraction diagnosis
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Shen, S.-H.;Ting, C.-Y.;Liu, C.-Y.;Cheng, H.;Liu, S.-I.;Lin, C.-T.; Shen, S.-H.; Ting, C.-Y.; Liu, C.-Y.; Cheng, H.; Liu, S.-I.; Lin, C.-T.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A 2×25 Gb/s clock and data recovery with background amplitude-locked loop
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Kao, C.-K.;Fu, K.-L.;Liu, S.-I.; Kao, C.-K.; Fu, K.-L.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A digital bang-bang phase-locked loop with bandwidth calibration
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Chiang, C.-H.;Huang, C.-C.;Liu, S.-I.; Chiang, C.-H.; Huang, C.-C.; Liu, S.-I.; SHEN-IUAN LIU |
顯示項目 31-40 / 144 (共15頁)
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