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Showing items 21-45 of 144 (6 Page(s) Totally)
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| 臺大學術典藏 |
2020-06-11T06:34:55Z |
A Subharmonically Injection-Locked All-Digital PLL Without Main Divider
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Zeng, K.-H.;Kuan, T.-K.;Liu, S.-I.; Zeng, K.-H.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:55Z |
A 10-bit 40-MS/s Time-Domain Two-Step ADC with Short Calibration Time
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Chen, L.-J.;Liu, S.-I.; Chen, L.-J.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 20-MHz to 3-GHz wide-range multiphase delay-locked loop
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Chuang, C.-N.;Liu, S.-I.; Chuang, C.-N.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 20-Gb/s transmitter with adaptive preemphasis in 65-nm CMOS technology
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Kao, S.-Y.;Liu, S.-I.; Kao, S.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 132.6-GHz phase-locked loop in 65 nm digital CMOS
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Lin, B.-Y.;Liu, S.-I.; Lin, B.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:54Z |
A 3-25 Gb/s four-channel receiver with noise-canceling TIA and power-scalable sLA
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Chien, Y.-H.;Fu, K.-L.;Liu, S.-I.; Chien, Y.-H.; Fu, K.-L.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:53Z |
A leakage-compensated PLL in 65-nm CMOS technology
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Hung, C.-C.;Liu, S.-I.; Hung, C.-C.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:52Z |
A 10-20 Gb/s CDR circuit with 6200ppm frequency tracking
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Huang, C.-C.;Tseng, K.-W.;Liu, S.-I.; Huang, C.-C.; Tseng, K.-W.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:52Z |
A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer with a Fast-Converging Correlation Loop
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Tseng, Y.-H.;Yeh, C.-W.;Liu, S.-I.; Tseng, Y.-H.; Yeh, C.-W.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:52Z |
A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis
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Su, W.-J.;Liu, S.-I.; Su, W.-J.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:51Z |
A Bang-Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques
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Kuan, T.-K.;Liu, S.-I.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:51Z |
A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS
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Hsieh, M.-H.; Chen, L.-H.; Liu, S.-I.; Chen, C.C.-P.; SHEN-IUAN LIU; Hsieh, M.-H.;Chen, L.-H.;Liu, S.-I.;Chen, C.C.-P. |
| 臺大學術典藏 |
2020-06-11T06:34:51Z |
A Voltage Multiplier With Adaptive Threshold Voltage Compensation
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Luo, Y.-S.;Liu, S.-I.; Luo, Y.-S.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:50Z |
A 33.6-to-33.8 Gb/s burst-mode CDR in 90 nm CMOS technology
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Cho, L.-C.;Lee, C.;Hung, C.-C.;Liu, S.-I.; Cho, L.-C.; Lee, C.; Hung, C.-C.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:50Z |
A 1.5 GHz all-digital spread-spectrum clock generator
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Lin, S.-Y.;Liu, S.-I.; Lin, S.-Y.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:49Z |
A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control
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Luo, Y.-S.;Lin, H.-H.;Liu, S.-I.; Luo, Y.-S.; Lin, H.-H.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:49Z |
A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing
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Lee, I.-T.;Chen, Y.-J.;Liu, S.-I.;Jou, C.-P.;Hsueh, F.-L.;Hsieh, H.-H.; Lee, I.-T.; Chen, Y.-J.; Liu, S.-I.; Jou, C.-P.; Hsueh, F.-L.; Hsieh, H.-H.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:49Z |
A silicon nanowire-based bio-sensing system with digitized outputs for acute myocardial infraction diagnosis
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Shen, S.-H.;Ting, C.-Y.;Liu, C.-Y.;Cheng, H.;Liu, S.-I.;Lin, C.-T.; Shen, S.-H.; Ting, C.-Y.; Liu, C.-Y.; Cheng, H.; Liu, S.-I.; Lin, C.-T.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A 2×25 Gb/s clock and data recovery with background amplitude-locked loop
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Kao, C.-K.;Fu, K.-L.;Liu, S.-I.; Kao, C.-K.; Fu, K.-L.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A digital bang-bang phase-locked loop with bandwidth calibration
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Chiang, C.-H.;Huang, C.-C.;Liu, S.-I.; Chiang, C.-H.; Huang, C.-C.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A 5-20 Gb/s power scalable adaptive linear equalizer using edge counting
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Lin, Y.-F.;Huang, C.-C.;Lee, J.-Y.M.;Chang, C.-T.;Liu, S.-I.; Lin, Y.-F.; Huang, C.-C.; Lee, J.-Y.M.; Chang, C.-T.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS
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Hsieh, C.-E.;Liu, S.-I.; Hsieh, C.-E.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:48Z |
A digital MDLL using switched biasing technique to reduce low-frequency phase noise
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Chiang, C.-H.;Huang, C.-C.;Kuan, T.-K.;Liu, S.-I.; Chiang, C.-H.; Huang, C.-C.; Kuan, T.-K.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:47Z |
A low-input-swing AC-DC voltage multiplier using Schottky diodes
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Luo, Y.-S.;Liu, S.-I.; Luo, Y.-S.; Liu, S.-I.; SHEN-IUAN LIU |
| 臺大學術典藏 |
2020-06-11T06:34:47Z |
A 0.43pJ/bit true random number generator
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Kuan, T.-K.;Chiang, Y.-H.;Liu, S.-I.; Kuan, T.-K.; Chiang, Y.-H.; Liu, S.-I.; SHEN-IUAN LIU |
Showing items 21-45 of 144 (6 Page(s) Totally)
1 2 3 4 5 6 > >>
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