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Institution Date Title Author
國立成功大學 2011-10 A Low-Flicker Noise Gate-Controlled Lateral-Vertical Bipolar Junction Transistor Array With 55-nm CMOS Technology Chen, Shuo-Mao; Fang, Yean-Kuen; Juang, Feng-Renn; Chen, Chia-Chung; Liu, Sally; Kuo, Chin-Wei; Chao, Chih-Ping; Tseng, Hua-Chou
國立臺灣大學 2006-10 Analysis of the Gate–Source/Drain Capacitance Behavior of a Narrow-Channel FD SOI NMOS Device Considering the 3-D Fringing Capacitances Using 3-D Simulation Chen, Chien-Chung; Kuo, James B.; Su, Ke-Wei; Liu, Sally
臺大學術典藏 2006-10 Analysis of the Gate–Source/Drain Capacitance Behavior of a Narrow-Channel FD SOI NMOS Device Considering the 3-D Fringing Capacitances Using 3-D Simulation Chen, Chien-Chung; Kuo, James B.; Su, Ke-Wei; Liu, Sally; Chen, Chien-Chung; Kuo, James B.; Su, Ke-Wei; Liu, Sally
國立臺灣大學 2006 Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation Chen, Chien-Chung; Kuo, J.B.; Su, Ke-Wei; Liu, Sally

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