| 臺大學術典藏 |
2005-03 |
CMOS Current-Mode Divider and Its Applications
|
Wei, Shui-Ken; Liu, Weihsing; Liu, Shen-Iuan; Wei, Shui-Ken; Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
CMOS wideband amplifiers using multiple inductive-series peaking technique
|
Wu, Chia-Hsin; Lee, Chih-Hun; Chen, Wei-Sheng; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
A single-path pulsewidth control loop with a built-in delay-locked loop
|
Han, Sung-Rung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
A wide-range multiphase delay-locked loop using mixed-mode VCDLs
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
Selective metal parallel shunting inductor and its VCO application
|
Wu, Chia-Hsin; Kuo, Chun-Yi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2005 |
CMOS Differential-Mode Exponential Voltage-To-Current Converter
|
Liu, Weihsing; Liu, Shen-Iuan; Wei, Shui-Ken |
| 淡江大學 |
2004-11 |
A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps
|
郭建宏; Kuo, Chien-hung; Liu, Shen-iuan |
| 國立臺灣大學 |
2004-08 |
A low power 5Gb/s transimpedance amplifier with dual feedback technique
|
Wang, I-Hsin; Liu, Chung-Shun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004-08 |
A 1.7~3.125Gbps clock and data recovery circuit using a gated frequency detector
|
Yang, Rong-Jyi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004-08 |
A 1.2V, 18mW, 10Gb/s SiGe transimpedance amplifier
|
Lee, Chihun; Wu, Chia-Hsin; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004-05 |
A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors
|
Wu, Chia-Hsin; Liao, Jieh-Wei; Liu, Shen-Iuan |
| 淡江大學 |
2004-04 |
Magnetic-to-digital converters using single-amplifier-based second-order delta-sigma modulators
|
郭建宏; Kuo, Chien-hung; Chen Shr-lung; Liu Shen-iuan |
| 國立臺灣大學 |
2004-03 |
A 500-MHz–1.25-GHz Fast-Locking Pulsewidth Control Loop With Presettable Duty Cycle
|
Han, Sung-Rung; Liu, Shen-Iuan |
| 臺大學術典藏 |
2004-03 |
A 500-MHz–1.25-GHz Fast-Locking Pulsewidth Control Loop With Presettable Duty Cycle
|
Han, Sung-Rung; Liu, Shen-Iuan; Han, Sung-Rung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004-02 |
A 2 GHz CMOS variable-gain amplifier with 50 dB linear-in-magnitude controlled gain range for 10GBase-LX4 Ethernet
|
Wu, Chia-Hsin; Liu, Chang-Shun; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
Low-voltage CMOS voltage-mode divider and its application
|
Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle
|
Han, Sung-Rung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
Low voltage and low power CMOS exponential-control variable-gain amplifier
|
Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
A Mixed-mode Synchronous Mirror Delay Insensitive to Supply and Load Variations
|
Sun, Chih-Hao; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
Magnetic-to-digital converters using single-amplifier-based second-order delta-sigma modulators
|
Kuo, Chien-Hung; Chen, Shr-Lung; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC
|
Liu, Ming-Huang; Huang, Kuo-Chan; Ou, Wei-Yang; Su, Tsung-Yi; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
Low-voltage and low-power CMOS voltage-to-current converter
|
Liu, Weihsing; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
A 3.125-Gb/s Clock and Data Recovery Circuit for the 10-Gbase-LX4 Ethernet
|
Yang, Rong-Jyi; Chen, Shang-Ping; Liu, Shen-Iuan |
| 國立臺灣大學 |
2004 |
Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection
|
Chang, Hsiang-Hui; Yang, Rong-Jyi; Liu, Shen-Iuan |
